lcm.tan.qmsg

代码是12864的vhdl驱动程序 并带有字库

{ "Info" "ITDB_TH_RESULT" "data\[5\] rst clk -2.315 ns register " "Info: th for register \"data\[5\]\" (data pin = \"rst\", clock pin = \"clk\") is -2.315 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 35 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 35; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcm.vhd" "" { Text "C:/Documents and Settings/admin/桌面/lcm/lcm.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns data\[5\] 2 REG LC_X7_Y5_N4 1 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X7_Y5_N4; Fanout = 1; REG Node = 'data\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk data[5] } "NODE_NAME" } } { "lcm.vhd" "" { Text "C:/Documents and Settings/admin/桌面/lcm/lcm.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk data[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout data[5] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lcm.vhd" "" { Text "C:/Documents and Settings/admin/桌面/lcm/lcm.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.217 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_61 20 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 20; PIN Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "lcm.vhd" "" { Text "C:/Documents and Settings/admin/桌面/lcm/lcm.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.244 ns) + CELL(0.914 ns) 4.290 ns data\[0\]~388 2 COMB LC_X7_Y5_N0 8 " "Info: 2: + IC(2.244 ns) + CELL(0.914 ns) = 4.290 ns; Loc. = LC_X7_Y5_N0; Fanout = 8; COMB Node = 'data\[0\]~388'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.158 ns" { rst data[0]~388 } "NODE_NAME" } } { "lcm.vhd" "" { Text "C:/Documents and Settings/admin/桌面/lcm/lcm.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.684 ns) + CELL(1.243 ns) 6.217 ns data\[5\] 3 REG LC_X7_Y5_N4 1 " "Info: 3: + IC(0.684 ns) + CELL(1.243 ns) = 6.217 ns; Loc. = LC_X7_Y5_N4; Fanout = 1; REG Node = 'data\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.927 ns" { data[0]~388 data[5] } "NODE_NAME" } } { "lcm.vhd" "" { Text "C:/Documents and Settings/admin/桌面/lcm/lcm.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.289 ns ( 52.90 % ) " "Info: Total cell delay = 3.289 ns ( 52.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.928 ns ( 47.10 % ) " "Info: Total interconnect delay = 2.928 ns ( 47.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.217 ns" { rst data[0]~388 data[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.217 ns" { rst rst~combout data[0]~388 data[5] } { 0.000ns 0.000ns 2.244ns 0.684ns } { 0.000ns 1.132ns 0.914ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk data[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout data[5] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.217 ns" { rst data[0]~388 data[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.217 ns" { rst rst~combout data[0]~388 data[5] } { 0.000ns 0.000ns 2.244ns 0.684ns } { 0.000ns 1.132ns 0.914ns 1.243ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 14 15:24:35 2009 " "Info: Processing ended: Tue Apr 14 15:24:35 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}