lcm.tan.rpt

代码是12864的vhdl驱动程序 并带有字库

; N/A   ; None         ; 7.153 ns   ; cs[0]~reg0       ; cs[0]       ; clk        ;
+-------+--------------+------------+------------------+-------------+------------+


+----------------------------------------------------------+
; tpd                                                      ;
+-------+-------------------+-----------------+------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To  ;
+-------+-------------------+-----------------+------+-----+
; N/A   ; None              ; 5.887 ns        ; clk  ; ena ;
+-------+-------------------+-----------------+------+-----+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To               ; To Clock ;
+---------------+-------------+-----------+------+------------------+----------+
; N/A           ; None        ; -2.315 ns ; rst  ; data[5]          ; clk      ;
; N/A           ; None        ; -2.323 ns ; rst  ; data_out[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.323 ns ; rst  ; data_out[1]~reg0 ; clk      ;
; N/A           ; None        ; -2.323 ns ; rst  ; data_out[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.323 ns ; rst  ; data_out[6]~reg0 ; clk      ;
; N/A           ; None        ; -2.768 ns ; rst  ; data[0]          ; clk      ;
; N/A           ; None        ; -2.768 ns ; rst  ; data[1]          ; clk      ;
; N/A           ; None        ; -3.189 ns ; rst  ; ctrl[1]~reg0     ; clk      ;
; N/A           ; None        ; -3.189 ns ; rst  ; cs[0]~reg0       ; clk      ;
; N/A           ; None        ; -3.189 ns ; rst  ; cs[1]~reg0       ; clk      ;
; N/A           ; None        ; -3.367 ns ; rst  ; data[7]          ; clk      ;
; N/A           ; None        ; -3.469 ns ; rst  ; data[2]          ; clk      ;
; N/A           ; None        ; -3.488 ns ; rst  ; data[3]          ; clk      ;
; N/A           ; None        ; -3.488 ns ; rst  ; data[4]          ; clk      ;
; N/A           ; None        ; -3.875 ns ; rst  ; data[6]          ; clk      ;
; N/A           ; None        ; -3.970 ns ; rst  ; data_out[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.970 ns ; rst  ; data_out[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.970 ns ; rst  ; data_out[5]~reg0 ; clk      ;
; N/A           ; None        ; -3.970 ns ; rst  ; data_out[7]~reg0 ; clk      ;
+---------------+-------------+-----------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 14 15:24:34 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lcm -c lcm
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 91.22 MHz between source register "y_cnt[0]" and destination register "data[4]" (period= 10.962 ns)
    Info: + Longest register to register delay is 10.253 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y4_N1; Fanout = 70; REG Node = 'y_cnt[0]'
        Info: 2: + IC(2.863 ns) + CELL(0.740 ns) = 3.603 ns; Loc. = LC_X10_Y7_N7; Fanout = 1; COMB Node = 'Mux39~150'
        Info: 3: + IC(2.618 ns) + CELL(0.914 ns) = 7.135 ns; Loc. = LC_X8_Y4_N6; Fanout = 1; COMB Node = 'Mux39~151'
        Info: 4: + IC(2.022 ns) + CELL(0.200 ns) = 9.357 ns; Loc. = LC_X7_Y6_N7; Fanout = 1; COMB Node = 'Mux47~142'
        Info: 5: + IC(0.305 ns) + CELL(0.591 ns) = 10.253 ns; Loc. = LC_X7_Y6_N8; Fanout = 1; REG Node = 'data[4]'
        Info: Total cell delay = 2.445 ns ( 23.85 % )
        Info: Total interconnect delay = 7.808 ns ( 76.15 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 35; CLK Node = 'clk'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X7_Y6_N8; Fanout = 1; REG Node = 'data[4]'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
        Info: - Longest clock path from clock "clk" to source register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 35; CLK Node = 'clk'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y4_N1; Fanout = 70; REG Node = 'y_cnt[0]'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "data_out[3]~reg0" (data pin = "rst", clock pin = "clk") is 4.524 ns
    Info: + Longest pin to register delay is 7.872 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 20; PIN Node = 'rst'
        Info: 2: + IC(2.235 ns) + CELL(0.914 ns) = 4.281 ns; Loc. = LC_X8_Y7_N7; Fanout = 8; COMB Node = 'data_out[0]~205'
        Info: 3: + IC(2.348 ns) + CELL(1.243 ns) = 7.872 ns; Loc. = LC_X4_Y6_N4; Fanout = 1; REG Node = 'data_out[3]~reg0'
        Info: Total cell delay = 3.289 ns ( 41.78 % )
        Info: Total interconnect delay = 4.583 ns ( 58.22 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk"