📄 ad.tan.rpt
字号:
; N/A ; 176.15 MHz ( period = 5.677 ns ) ; count[0] ; count[5] ; clk ; clk ; None ; None ; 4.968 ns ;
; N/A ; 177.21 MHz ( period = 5.643 ns ) ; count[2] ; count[3] ; clk ; clk ; None ; None ; 4.934 ns ;
; N/A ; 179.37 MHz ( period = 5.575 ns ) ; count[3] ; count[6] ; clk ; clk ; None ; None ; 4.866 ns ;
; N/A ; 180.67 MHz ( period = 5.535 ns ) ; count[4] ; count[6] ; clk ; clk ; None ; None ; 4.826 ns ;
; N/A ; 181.32 MHz ( period = 5.515 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 4.806 ns ;
; N/A ; 182.58 MHz ( period = 5.477 ns ) ; count[0] ; count[3] ; clk ; clk ; None ; None ; 4.768 ns ;
; N/A ; 183.49 MHz ( period = 5.450 ns ) ; count[5] ; count[7] ; clk ; clk ; None ; None ; 4.741 ns ;
; N/A ; 183.65 MHz ( period = 5.445 ns ) ; count[6] ; count[0] ; clk ; clk ; None ; None ; 4.736 ns ;
; N/A ; 183.69 MHz ( period = 5.444 ns ) ; count[6] ; count[6] ; clk ; clk ; None ; None ; 4.735 ns ;
; N/A ; 184.26 MHz ( period = 5.427 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 4.718 ns ;
; N/A ; 188.22 MHz ( period = 5.313 ns ) ; count[1] ; count[2] ; clk ; clk ; None ; None ; 4.604 ns ;
; N/A ; 190.04 MHz ( period = 5.262 ns ) ; count[2] ; count[0] ; clk ; clk ; None ; None ; 4.553 ns ;
; N/A ; 193.69 MHz ( period = 5.163 ns ) ; count[7] ; count[1] ; clk ; clk ; None ; None ; 4.454 ns ;
; N/A ; 193.76 MHz ( period = 5.161 ns ) ; count[7] ; count[2] ; clk ; clk ; None ; None ; 4.452 ns ;
; N/A ; 193.99 MHz ( period = 5.155 ns ) ; count[5] ; count[6] ; clk ; clk ; None ; None ; 4.446 ns ;
; N/A ; 194.06 MHz ( period = 5.153 ns ) ; count[7] ; count[7] ; clk ; clk ; None ; None ; 4.444 ns ;
; N/A ; 194.17 MHz ( period = 5.150 ns ) ; count[7] ; clk_10 ; clk ; clk ; None ; None ; 4.441 ns ;
; N/A ; 195.73 MHz ( period = 5.109 ns ) ; count[6] ; count[7] ; clk ; clk ; None ; None ; 4.400 ns ;
; N/A ; 195.73 MHz ( period = 5.109 ns ) ; count[1] ; count[0] ; clk ; clk ; None ; None ; 4.400 ns ;
; N/A ; 198.61 MHz ( period = 5.035 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 4.326 ns ;
; N/A ; 199.76 MHz ( period = 5.006 ns ) ; count[0] ; count[2] ; clk ; clk ; None ; None ; 4.297 ns ;
; N/A ; 202.76 MHz ( period = 4.932 ns ) ; count[4] ; count[4] ; clk ; clk ; None ; None ; 4.223 ns ;
; N/A ; 206.74 MHz ( period = 4.837 ns ) ; count[3] ; count[3] ; clk ; clk ; None ; None ; 4.128 ns ;
; N/A ; 216.36 MHz ( period = 4.622 ns ) ; count[0] ; clk_10 ; clk ; clk ; None ; None ; 3.913 ns ;
; N/A ; 221.68 MHz ( period = 4.511 ns ) ; count[6] ; count[1] ; clk ; clk ; None ; None ; 3.802 ns ;
; N/A ; 221.78 MHz ( period = 4.509 ns ) ; count[6] ; count[2] ; clk ; clk ; None ; None ; 3.800 ns ;
; N/A ; 222.32 MHz ( period = 4.498 ns ) ; count[6] ; clk_10 ; clk ; clk ; None ; None ; 3.789 ns ;
; N/A ; 222.52 MHz ( period = 4.494 ns ) ; count[5] ; count[5] ; clk ; clk ; None ; None ; 3.785 ns ;
; N/A ; 223.56 MHz ( period = 4.473 ns ) ; count[2] ; count[2] ; clk ; clk ; None ; None ; 3.764 ns ;
; N/A ; 228.15 MHz ( period = 4.383 ns ) ; count[5] ; count[0] ; clk ; clk ; None ; None ; 3.674 ns ;
; N/A ; 228.78 MHz ( period = 4.371 ns ) ; count[2] ; count[1] ; clk ; clk ; None ; None ; 3.662 ns ;
; N/A ; 228.89 MHz ( period = 4.369 ns ) ; count[2] ; clk_10 ; clk ; clk ; None ; None ; 3.660 ns ;
; N/A ; 237.19 MHz ( period = 4.216 ns ) ; count[1] ; clk_10 ; clk ; clk ; None ; None ; 3.507 ns ;
; N/A ; 248.14 MHz ( period = 4.030 ns ) ; count[3] ; count[0] ; clk ; clk ; None ; None ; 3.321 ns ;
; N/A ; 254.39 MHz ( period = 3.931 ns ) ; clk_10 ; clk_10 ; clk ; clk ; None ; None ; 3.222 ns ;
; N/A ; 258.20 MHz ( period = 3.873 ns ) ; count[4] ; count[0] ; clk ; clk ; None ; None ; 3.164 ns ;
; N/A ; 289.94 MHz ( period = 3.449 ns ) ; count[5] ; count[1] ; clk ; clk ; None ; None ; 2.740 ns ;
; N/A ; 290.11 MHz ( period = 3.447 ns ) ; count[5] ; count[2] ; clk ; clk ; None ; None ; 2.738 ns ;
; N/A ; 291.04 MHz ( period = 3.436 ns ) ; count[5] ; clk_10 ; clk ; clk ; None ; None ; 2.727 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[1] ; clk ; clk ; None ; None ; 2.430 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[2] ; clk ; clk ; None ; None ; 2.429 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; clk_10 ; clk ; clk ; None ; None ; 2.428 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[4] ; count[1] ; clk ; clk ; None ; None ; 2.230 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[4] ; count[2] ; clk ; clk ; None ; None ; 2.228 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[4] ; clk_10 ; clk ; clk ; None ; None ; 2.217 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+-----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+-----+------------+
; N/A ; None ; 9.090 ns ; clk_10 ; sck ; clk ;
+-------+--------------+------------+--------+-----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Apr 21 15:31:29 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ad -c ad
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 164.02 MHz between source register "count[7]" and destination register "count[0]" (period= 6.097 ns)
Info: + Longest register to register delay is 5.388 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N7; Fanout = 2; REG Node = 'count[7]'
Info: 2: + IC(2.079 ns) + CELL(0.740 ns) = 2.819 ns; Loc. = LC_X9_Y6_N5; Fanout = 6; COMB Node = 'Equal0~65'
Info: 3: + IC(1.978 ns) + CELL(0.591 ns) = 5.388 ns; Loc. = LC_X8_Y6_N9; Fanout = 4; REG Node = 'count[0]'
Info: Total cell delay = 1.331 ns ( 24.70 % )
Info: Total interconnect delay = 4.057 ns ( 75.30 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.681 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y6_N9; Fanout = 4; REG Node = 'count[0]'
Info: Total cell delay = 2.081 ns ( 56.53 % )
Info: Total interconnect delay = 1.600 ns ( 43.47 % )
Info: - Longest clock path from clock "clk" to source register is 3.681 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X9_Y6_N7; Fanout = 2; REG Node = 'count[7]'
Info: Total cell delay = 2.081 ns ( 56.53 % )
Info: Total interconnect delay = 1.600 ns ( 43.47 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "sck" through register "clk_10" is 9.090 ns
Info: + Longest clock path from clock "clk" to source register is 3.681 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X9_Y6_N6; Fanout = 2; REG Node = 'clk_10'
Info: Total cell delay = 2.081 ns ( 56.53 % )
Info: Total interconnect delay = 1.600 ns ( 43.47 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Longest register to pin delay is 5.033 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N6; Fanout = 2; REG Node = 'clk_10'
Info: 2: + IC(2.711 ns) + CELL(2.322 ns) = 5.033 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'sck'
Info: Total cell delay = 2.322 ns ( 46.14 % )
Info: Total interconnect delay = 2.711 ns ( 53.86 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Tue Apr 21 15:31:29 2009
Info: Elapsed time: 00:00:00
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