dma2.c

支持三星原产的S3C24A0开发板

/*****************************************
  NAME: Worst DMA
  DESC: Worst DMA memory2memory test
  	Ch1,2,3,4 are operated simultaneously
  HISTORY:
  2003.12.29 :draft ver 0.0
 *****************************************/

#include <string.h>
#include "def.h"
#include "option.h"
#include "24a0addr.h"
#include "24a0lib.h"
#include "24a0slib.h" 

static void __irq WorstDmaDone(void);


void DMA0123_M2M(int ch,int srcAddr,int dstAddr,int tc,int dsz,int burst);

typedef struct tagDMA
{
    volatile U32 DISRC;	    //0x0
    volatile U32 DISRCC;    //0x4
    volatile U32 DIDST;	    //0x8
    volatile U32 DIDSTC;    //0xc
    volatile U32 DCON;	    //0x10
    volatile U32 DSTAT;	    //0x14
    volatile U32 DCSRC;	    //0x18
    volatile U32 DCDST;	    //0x1c
    volatile U32 DMASKTRIG; //0x20
}DMA;


static volatile int dmaDone;

void Test_DMAWorst(void)
{
    int i;

    Uart_Printf("[DMA0123 MEM2MEM Worst Test]\n");
    dmaDone=0;

    for(i=_NONCACHE_STARTADDRESS;i<_NONCACHE_STARTADDRESS+0x800000;i+=4)
    {
    	*((U32 *)i)=i^0x55aa5aa5;
		//*((U32 *)i)=i;
    }

    //Start DMA ch0,1,2,3 simultaneously.
    //DMA0123_M2M(0,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x80000,0x80000,0,0); //byte,single
   	DMA0123_M2M(0, _NONCACHE_STARTADDRESS, _NONCACHE_STARTADDRESS + 0x100000, 0xfffff,0, 0);
}




void DMA0123_M2M(int ch,int srcAddr,int dstAddr,int tc,int dsz,int burst)
{
    int i,time;
    volatile U32 memSum0=0,memSum1=0;
    DMA *pDMA;
    int length;
    
    length=tc*(burst ? 4:1)*((dsz==0)+(dsz==1)*2+(dsz==2)*4);
    //rINTMSK &=~(BIT_DMA);//sjs
    //pISR_DMA=(int)DmaDone;    
    
    switch(ch)
    {
    case 0:
    	pISR_DMA=(int)WorstDmaDone;
	rINTSUBMSK &=~(BIT_SUB_DMA0); 
	rINTMSK &=~(BIT_DMA);
    	pDMA=(void *)0x40400000;
    	break;
    case 1:
    	pISR_DMA=(int)WorstDmaDone;
	rINTSUBMSK &=~(BIT_SUB_DMA1); 
    	rINTMSK &=~(BIT_DMA);  
	pDMA=(void *)0x40500000;
    	break;
    case 2:
	pISR_DMA=(int)WorstDmaDone;
	rINTSUBMSK &=~(BIT_SUB_DMA2); 
	rINTMSK &=~(BIT_DMA);
    	pDMA=(void *)0x40600000;
	break;
    case 3:
        pISR_DMA=(int)WorstDmaDone;
	rINTSUBMSK &=~(BIT_SUB_DMA3); 
       	rINTMSK &=~(BIT_DMA);
	pDMA=(void *)0x40700000;
        break;
    }
                                                                                                                            
    pDMA->DISRC=srcAddr;
    pDMA->DISRCC=(0<<1)|(0<<0); // inc,AHB
    pDMA->DIDST=dstAddr;
    pDMA->DIDSTC=(0<<1)|(0<<0); // inc,AHB
    pDMA->DCON=(1<<31)|(1<<30)|(1<<29)|(burst<<28)|(1<<27)|(0<<23)|(1<<22)|(dsz<<20)|(tc);

      		//HS,AHB,TC interrupt,whole, SW request mode,relaod off
//    pDMA->DMASKTRIG=(1<<1)|1; //DMA on, SW_TRIG

/*
	for(i=srcAddr;i<srcAddr+length;i+=4)
		{
		*((U32 *)i)=i;
		memSum0+=i;
		}
*/
    Uart_Printf("#");

    switch(ch)
    {
    case 0:
        //DMA Ch 1
		//DMA0123_M2M(1,_NONCACHE_STARTADDRESS+0x20000,_NONCACHE_STARTADDRESS+0xa0000,0x40000,1,0); //halfword,single
		DMA0123_M2M(1, _NONCACHE_STARTADDRESS+0x40000, _NONCACHE_STARTADDRESS + 0x140000, 0xfffff,1, 0);
		break;
    case 1:
    	//DMA Ch 2
    	//DMA0123_M2M(2,_NONCACHE_STARTADDRESS+0x40000,_NONCACHE_STARTADDRESS+0xc0000,0x20000,2,0); //word,single
		DMA0123_M2M(2, _NONCACHE_STARTADDRESS+0x80000, _NONCACHE_STARTADDRESS + 0x180000, 0xfffff,2, 0);
		break;
    case 2:
        //DMA Ch 3
        //DMA0123_M2M(3,_NONCACHE_STARTADDRESS+0x60000,_NONCACHE_STARTADDRESS+0xe0000,0x8000,2,1); //word,burst
   		DMA0123_M2M(3, _NONCACHE_STARTADDRESS+0xC0000, _NONCACHE_STARTADDRESS + 0x1C0000, 0xfffff,2, 1);
		break;
    case 3:
    	rDMASKTRIG0=(1<<1)|1;
    	rDMASKTRIG1=(1<<1)|1;
    	rDMASKTRIG2=(1<<1)|1;
    	rDMASKTRIG3=(1<<1)|1;
	break;	
	default:
		break;
    }
    
	for(i=srcAddr;i<(srcAddr+length);i+=4)
		{
		memSum0+=*((U32 *)i);
		}

	while(dmaDone!=0xf);
  
    rINTMSK=BIT_ALLMSK;
    rINTSUBMSK=BIT_SUB_ALLMSK;

	
	for(i=dstAddr;i<dstAddr+length;i+=4)
		{
		memSum1+=*((U32 *)i);
		}

    Uart_Printf("\nDMA%d %8xh->%8xh,size=%xh(tc=%xh),dsz=%d,burst=%d\n",ch,srcAddr,dstAddr,length,tc,dsz,burst);
    Uart_Printf("memSum0=%x,memSum1=%x\n",memSum0,memSum1);
    if(memSum0==memSum1)
    	Uart_Printf("DMA test result--------------------------------------O.K.\n");
    else 
    	Uart_Printf("DMA test result--------------------------------------ERROR!!!\n");

}


static void __irq WorstDmaDone(void)
{
    //int i;
    rINTSUBMSK|=(BIT_SUB_DMA0|BIT_SUB_DMA1|BIT_SUB_DMA2|BIT_SUB_DMA3);
    rINTMSK|=(BIT_DMA);
    //i=rSUBSRCPND;
    if(rSUBSRCPND&(1<<25)) 
    {
    	rSUBSRCPND=BIT_SUB_DMA0;
	dmaDone+=1;
    }
    else if(rSUBSRCPND&(1<<26)) 
    {
    	rSUBSRCPND=BIT_SUB_DMA1;
	dmaDone+=2;
    }
    else if(rSUBSRCPND&(1<<27)) 
    {
    	rSUBSRCPND=BIT_SUB_DMA2;
	dmaDone+=4;
    }
    else if(rSUBSRCPND&(1<<28)) 
    {
    	rSUBSRCPND=BIT_SUB_DMA3;
	dmaDone+=8;
    }
    else
    {
    	Uart_Printf("DMA SUB INT Fail\n");
    }
    ClearPending(BIT_DMA);
    rINTMSK &= ~(BIT_DMA);
    rINTSUBMSK &= ~(BIT_SUB_DMA0|BIT_SUB_DMA1|BIT_SUB_DMA2|BIT_SUB_DMA3);
}