iis.c

支持三星原产的S3C24A0开发板

/*	  
    //ChangeMPllValue(82,4,1);  //FCLK=90.316800MHz, PCLK=45.158400MHz <-- 5.644800MHz*8
    //ChangeClockDivider(0,1);		  // 1:1:2    
    //ChangeSdramParameter(HCLK); 
    //Uart_Init(45158400,115200);
    //IIS 256fs Initialize
    if(fs==44100)               //11.2896MHz(256fs)
    {
        rIISPSR = (2<<5) + 2;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)  <- (PCLK = 33.857142MHz)/3 = 11.2896MHz      
    }
    else if(fs==22050)                        //fs=22050, 5.644800MHz(256fs)
    {
        rIISPSR = (7<<5) + 7;   //Prescaler A,B=7 <- (PCLK = 45MHz)/8 = 5.625MHz    
    }
    rIISMOD = (0<<8) + (1<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
      //Master,Rx,L-ch=low,IIS,16bit ch,CDCLK=256fs,IISCLK=32fs    
    rIISCON = (0<<5) + (1<<4) + (1<<3) + (0<<2) + (1<<1);
      //Tx DMA disable,Rx DMA enable,Tx idle,Rx not idle,prescaler enable,stop
*/
    rIISFCON = (1<<14) + (1<<12);     //Rx DMA,Rx FIFO --> start piling....

    Uart_Printf("Press any key to start record!!!\n");
    Uart_Getch();
    Uart_Printf("Recording...\n");

      //Rx start
    rIISCON |= 0x1;

    while(!Rec_Done);

    rINTSUBMSK |= BIT_SUB_DMA0;
    rINTMSK  |= BIT_DMA;
    Rec_Done = 0;

      //IIS Stop
    Delay(10);                          //For end of H/W Rx
    rIISCON     = 0x0;                  //IIS stop
    rDMASKTRIG0 = (1<<2);               //DMA0 stop
    rIISFCON    = 0x0;                  //For FIFO flush
    
    Uart_Printf("End of Record!!!\n");
    Uart_Printf("Press any key to play recorded data\n");
    Uart_Printf("If you want to mute or no mute push the 'EIN0' key repeatedly\n");
    Uart_Getch();

    size = REC_LEN * 2;
//  size = (volatile unsigned int)rec_buf - 0x31000000 + 2;
    Uart_Printf("Size = %d\n",size);
//  rec_buf = (unsigned short *)0x31000000;

    Init1341(PLAY);

    pISR_DMA = (unsigned)DMA1_IISSDO_Done;

    rEINTPEND = 0xffffff;
    rSRCPND = BIT_EINT0_2; //to clear the previous pending states
    rINTPND = BIT_EINT0_2;

    rEINTMASK=~(1<<0);		
    rINTMSK   = ~(BIT_DMA| BIT_EINT0_2);
    rINTSUBMSK = ~(BIT_SUB_DMA1);
    
      //DMA1 Initialize
    rDISRCC1 = (0<<1) + (0<<0);                         //AHB, Increment
    rDISRC1  = (int)rec_buf;                            //0x31000000
    rDIDSTC1 = (Intr_Time_Arg<<2) + (1<<1) + (1<<0);                 //The destination is in the peripheral bus(APB), Fixed  
    rDIDST1  = ((U32)IISFIFO);                          //IISFIFO
    rDCON1   = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(2<<24)+(1<<23)+(0<<22)+(1<<20)+(size/2);
      //Handshake, sync PCLK, TC int, single tx, single service, I2SSDO, I2S request, 
      //Auto-reload, half-word, size/2
    rDMASKTRIG1 = (0<<2)+(1<<1)+0;    //No-stop, DMA2 channel on, No-sw trigger 

      //IIS 384fs Initialize
    if(fs==44100)               //16.9344MHz(384fs)
    {
        rIISPSR = (2<<5) + 2;   //Prescaler A,B=2 <- FCLK 203.2128MHz(1:2:4)  <- (PCLK = 50.8032MHz)/3 = 16.9344MHz      
    }
    else if(fs==22050)       //8.4672MHz(384fs)
    {
        rIISPSR = (5<<5) + 5;   //Prescaler A,B=5 <- (PCLK = 50.8032MHz)/6 = 8.4672MHz    
    }
    rIISCON = (1<<5) + (1<<2) + (1<<1);        
      //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
    rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (1<<2) + (1<<0);      
      //Master mode[8],Tx mode[7:6],Low for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 384fs[2],IISCLK 32fs[1:0]
	  
/*	  
    //ChangeMPllValue(82,4,1);  //FCLK=90.316800MHz, PCLK=45.158400MHz <-- 5.644800MHz*8
    //ChangeClockDivider(0,1);		  // 1:1:2    
    //ChangeSdramParameter(HCLK); 
    //Uart_Init(45158400,115200);
      //IIS 256fs Initialize
    if(fs==44100)               //11.2896MHz(256fs)
    {
        rIISPSR = (2<<5) + 2;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)  <- (PCLK = 33.857142MHz)/3 = 11.2896MHz      
    }
    else if(fs==22050)                        //fs=22050, 5.644800MHz(256fs)
    {
        rIISPSR = (7<<5) + 7;   //Prescaler A,B=7 <- (PCLK = 45MHz)/8 = 5.625MHz    
    }
    rIISCON = (1<<5) + (1<<2) + (1<<1);         
      //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
    rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
      //Master mode[8],Tx mode[7:6],Low for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
*/
    rIISFCON = (1<<15) + (1<<13);       //Tx DMA,Tx FIFO --> start piling....

    Uart_Printf("Press any key to exit!!!\n");

    rIISCON |= 0x1;                   //IIS Tx Start
    while(!Uart_GetKey());

      //IIS Tx Stop
    Delay(10);               //For end of H/W Tx
    rIISCON     = 0x0;       //IIS stop
    rDMASKTRIG1 = (1<<2);    //DMA1 stop
    rIISFCON    = 0x0;       //For FIFO flush

    size = 0;

    rGPCON_M = save_GPCON_M;
    rGPCON_L = save_GPCON_L;	
    rGPPU = save_GPPU;


    rINTSUBMSK|=(BIT_SUB_DMA1);
    rINTMSK |= (BIT_DMA | BIT_EINT0_2);
    rEINTMASK=0xffffff;
	
    //(0,0)=1:1:1, (0,1)=1:1:2, (1,0)=1:2:2 (1,1)=1:2:4, (2,0)=1:4:5, (2,1)=1:4:8
    ChangeClockDivider(1,1);
    //(76,4,1)=84Mhz,  (93,4,1)=101Mhz, (54,1,1)=124Mhz, (68,4,0)=152Mhz
    //(93,4,0)=202Mhz, (47,1,0)=220Mhz, (72,2,0)=240Mhz, (79,2,0)=261Mhz
    //(195,10,0)=203MHz, (60,2,0)=204MHz	
    //ChangeMPllValue(195,10,0);// FCLK=203MHz   
    ChangeMPllValue(60,2,0);// FCLK=204Mhz 
    ChangeSdramParameter(HCLK);
    Uart_Init(0,115200);

    mute = 1;
}


//******************[ Init1341 ]**************************************
void Init1341(char mode)
{
    //Port Initialize
//----------------------------------------------------------
//   GPCON_M GROUP
//Ports  :   GP17    GP16   GP15  
//Signal :  L3MODE L3CLOCK L3DATA
//Setting:   OUTPUT OUTPUT OUTPUT 
//           [13:12]   [11:10]  [9:8]
//Binary :     01  ,   01    01 
//----------------------------------------------------------    
    rGPDAT = rGPDAT & ~(L3M|L3C|L3D) |(L3M|L3C); //Start condition : L3M=H, L3C=H
    rGPPU  = rGPPU  & ~(0x7<<15) |(0x7<<15);       //The pull up function is disabled GPUP[17:15] 0011 1000 0000 0000 0000    
    rGPCON_M = rGPCON_M & ~(0x3f<<8) |(0x15<<8);     //GPCON_M[13:8]=Output(L3MODE):Output(L3CLOCK):Output(L3DATA)

      //384fs L3 Interface
    _WrL3Addr(0x14 + 2);     //STATUS (000101xx+10)
    _WrL3Data(0x50,0);       //0,1,01,000,0 : Reset,384fs,no DCfilter,iis
    
    _WrL3Addr(0x14 + 2);     //STATUS (000101xx+10)
    _WrL3Data(0x10,0);       //0,0,01,000,0 : No reset,384fs,no DCfilter,iis  
/*
      //256fs L3 Interface
    _WrL3Addr(0x14 + 2);     //STATUS (000101xx+10)
    _WrL3Data(0x60,0);       //0,1,10,000,0 : Reset,256fs,no DCfilter,iis
    
    _WrL3Addr(0x14 + 2);     //STATUS (000101xx+10)
    _WrL3Data(0x20,0);       //0,0,10,000,0 : No reset,256fs,no DCfilter,iis
*/     
    _WrL3Addr(0x14 + 2);     //STATUS (000101xx+10)
    _WrL3Data(0x81,0);        // 1,0,0,0,0,0,01 : OGS=0,IGS=0,ADC_NI,DAC_NI,sngl speed,AoffDon    
   
      //record
    if(mode)
    {
        _WrL3Addr(0x14 + 2);     //STATUS (000101xx+10)
        _WrL3Data(0xa2,0);        // 1,0,1,0,0,0,10 : OGS=0,IGS=1,ADC_NI,DAC_NI,sngl speed,AonDoff

        _WrL3Addr(0x14 + 0);     //DATA0 (000101xx+00)
        _WrL3Data(0xc2,0);        //11000,010  : DATA0, Extended addr(010) 
        _WrL3Data(0x4d,0);        //010,011,01 : DATA0, MS=9dB, Ch1=on Ch2=off, 
        
//        _WrL3Addr(0x14 + 0);    //DATA0 (000101xx+00)
//        _WrL3Data(0xa4,0);       //10,1,10,0,00 : after, 44.1KHz de-emp, no mute, flat      

//        _WrL3Data(0x4c,0);        //010,011,00 : DATA0, MS=9dB, DD Mode,            
//        _WrL3Data(0x4e,0);        //010,011,10 : DATA0, MS=9dB, Ch1=off Ch2=on, 
//        _WrL3Data(0xaf,0);        
//        _WrL3Data(0x4f,0);        //010,011,11 : DATA0, MS=9dB, Mixer Mode, 
    }   
}

//===================================================================
void ChangeDMA1(void)
{
    if(which_Buf)
    {
        rDISRCC1 = (0<<1) + (0<<0);                         //AHB, Increment
        rDISRC1  = (int)(Buf + 0x30);                       //0x11000030~(Remove header)
    }
    else
    {
        rDISRCC1 = (0<<1) + (0<<0);                         //AHB, Increment
        rDISRC1  = (int)(Buf + 0x30+(size/2));              //0x11000030 + size/2~
    }
}

//===================================================================
void IIS_PortSetting(void)
{
    //Port Initialize
//----------------------------------------------------------
//   GPCON_M GROUP
//Ports  :   GP17    GP16   GP15  
//Signal :  L3MODE L3CLOCK L3DATA
//Setting:   OUTPUT OUTPUT OUTPUT 
//          [13:12]  [11:10]  [9:8]   
//Binary :     01  ,   01    01 
//----------------------------------------------------------      
    rGPPU  = rGPPU  & ~(0x7<<15) |(0x7<<15);       //The pull up function is disabled GPUP[17:15] 0011 1000 0000 0000 0000    
    rGPCON_M = rGPCON_M & ~(0x3f<<8) |(0x15<<8);     //GPCON_M[13:8]=Output(L3MODE):Output(L3CLOCK):Output(L3DATA)

//External INT 0
//    rGPUP  = rGPUP  & ~(0x1<<0) |(0x1<<0);       //The pull up function is disabled GPUP[0]   
    rGPCON_L = (rGPCON_L & 0x3ffffc)|(0x2<<0);
    rEXTINTC0 = rEXTINTC0 & ~(7<<0) | (0x4<<0);     //EINT0=rising edge triggered  

//External INT 9
//    rGPPU  = rGPPU  & ~(0x1<<9) |(0x1<<9);       //The pull up function is disabled GPPU[9]   
//    rGPCON_L = (rGPCON_L & 0x3ffffc)|(0x2<<0);
//    rGPCON_L = rGPCON_L & ~(0x3<<18)|(0x2<<18);
//    rEXTINTC1 = rEXTINTC1 & ~(0x7<<24) | (0x4<<24);     //EINT9=rising edge triggered  
	
//----------------------------------------------------------
//   External Port Pull-up 
//    rENPU = rENPU&~(1<<9) | (1<<9); //The pull up function is disabled rENPU[9]
//    rOENinSLEEP0 = rOENinSLEEP0&~(1<<9) | (1<<9);


}

//===================================================================
void _WrL3Addr(U8 data)
{       
    S32 i,j;

    rGPDAT  = rGPDAT & ~(L3D | L3M | L3C) | L3C;      //L3D=L, L3M=L(in address mode), L3C=H

    for(j=0;j<4;j++);                   //tsu(L3) > 190ns

    for(i=0;i<8;i++)                    //LSB first
    {
        if(data & 0x1)                  //If data's LSB is 'H'
        {
            rGPDAT &= ~L3C;            //L3C=L
            rGPDAT |= L3D;             //L3D=H             
            
            for(j=0;j<4;j++);           //tcy(L3) > 500ns
            
            rGPDAT |= L3C;             //L3C=H
            rGPDAT |= L3D;             //L3D=H
            
            for(j=0;j<4;j++);           //tcy(L3) > 500ns
        }
        else                            //If data's LSB is 'L'
        {
            rGPDAT &= ~L3C;            //L3C=L
            rGPDAT &= ~L3D;            //L3D=L
            
            for(j=0;j<4;j++);           //tcy(L3) > 500ns
            
            rGPDAT |= L3C;             //L3C=H
            rGPDAT &= ~L3D;            //L3D=L
            
            for(j=0;j<4;j++);           //tcy(L3) > 500ns            
        }
        data >>= 1;
    }
    rGPDAT  = rGPDAT & ~(L3D | L3M | L3C) | (L3C | L3M);       //L3M=H,L3C=H   
}

//===================================================================
void _WrL3Data(U8 data,int halt)
{
    S32 i,j;

    if(halt)
    {
        rGPDAT  = rGPDAT & ~(L3D | L3M | L3C) | L3C;   //L3C=H(while tstp, L3 interface halt condition)        
        for(j=0;j<4;j++);                                //tstp(L3) > 190ns
    }

    rGPDAT  = rGPDAT & ~(L3D | L3M | L3C) | (L3C | L3M);   //L3M=H(in data transfer mode)        
    for(j=0;j<4;j++);                                        //tsu(L3)D > 190ns

    for(i=0;i<8;i++)
    {
        if(data & 0x1)                   //if data's LSB is 'H'
        {
           rGPDAT &= ~L3C;              //L3C=L