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📄 mmu.txt

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; generated by ARM C Compiler, ADS1.2 [Build 805]

; commandline [-errors .\err\mmu.err -O0 -asm -g+ -cpu 5TEJ -fs -Wd -Ec -I.\include "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
                          CODE32

                          AREA ||.text||, CODE, READONLY

                  MMU_SetMTT PROC
;;;107    void MMU_SetMTT(U32 vaddrStart,U32 vaddrEnd,U32 paddrStart,U32 attr)
;;;108    {
000000  e92d4070          STMFD    sp!,{r4-r6,lr}
;;;109        U32 *pTT;
;;;110        U32 i,nSec;
;;;111        pTT=(U32 *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
000004  e1a05a20          MOV      r5,r0,LSR #20
000008  e59f6200          LDR      r6,|L1.528|
00000c  e086e105          ADD      lr,r6,r5,LSL #2
;;;112        nSec=(vaddrEnd>>20)-(vaddrStart>>20);
000010  e1a05a21          MOV      r5,r1,LSR #20
000014  e0454a20          SUB      r4,r5,r0,LSR #20
;;;113        for(i=0;i<=nSec;i++)*pTT++=attr |(((paddrStart>>20)+i)<<20);
000018  e3a0c000          MOV      r12,#0
                  |L1.28|
00001c  e15c0004          CMP      r12,r4
000020  8a000006          BHI      |L1.64|
000024  ea000001          B        |L1.48|
                  |L1.40|
000028  e28cc001          ADD      r12,r12,#1
00002c  eafffffa          B        |L1.28|
                  |L1.48|
000030  e08c5a22          ADD      r5,r12,r2,LSR #20
000034  e1835a05          ORR      r5,r3,r5,LSL #20
000038  e48e5004          STR      r5,[lr],#4
00003c  eafffff9          B        |L1.40|
;;;114    }
                  |L1.64|
000040  e8bd8070          LDMFD    sp!,{r4-r6,pc}
                          ENDP

                  MMU_Init PROC
;;;21     void MMU_Init(void)
;;;22     {
000044  e92d4038          STMFD    sp!,{r3-r5,lr}
;;;23         int i,j;
;;;24         //========================== IMPORTANT NOTE =========================
;;;25         //The current stack and code area can't be re-mapped in this routine.
;;;26         //If you want memory map mapped freely, your own sophiscated MMU
;;;27         //initialization code is needed.
;;;28         //===================================================================
;;;29     
;;;30         MMU_DisableDCache();
000048  ebfffffe          BL       MMU_DisableDCache
;;;31         MMU_DisableICache();
00004c  ebfffffe          BL       MMU_DisableICache
;;;32         for(i=0;i<4;i++)
000050  e3a05000          MOV      r5,#0
                  |L1.84|
000054  e3550004          CMP      r5,#4
000058  aa00000d          BGE      |L1.148|
00005c  ea000001          B        |L1.104|
                  |L1.96|
000060  e2855001          ADD      r5,r5,#1
000064  eafffffa          B        |L1.84|
;;;33         	for(j=0;j<128;j++)
                  |L1.104|
000068  e3a04000          MOV      r4,#0
                  |L1.108|
00006c  e3540080          CMP      r4,#0x80
000070  aa000006          BGE      |L1.144|
000074  ea000001          B        |L1.128|
                  |L1.120|
000078  e2844001          ADD      r4,r4,#1
00007c  eafffffa          B        |L1.108|
;;;34         	    MMU_CleanInvalidateDCacheSET((i<<30)|(j<<5));
                  |L1.128|
000080  e1a01f05          MOV      r1,r5,LSL #30
000084  e1810284          ORR      r0,r1,r4,LSL #5
000088  ebfffffe          BL       MMU_CleanInvalidateDCacheSET
00008c  eafffff9          B        |L1.120|
                  |L1.144|
000090  eafffff2          B        |L1.96|
;;;35         MMU_InvalidateICache();
                  |L1.148|
000094  ebfffffe          BL       MMU_InvalidateICache
;;;36         #if 0
;;;37         //To complete MMU_Init() fast, Icache may be turned on here.
;;;38         MMU_EnableICache(); 
;;;39         #endif
;;;40         MMU_DisableMMU();
000098  ebfffffe          BL       MMU_DisableMMU
;;;41         MMU_InvalidateTLB();
00009c  ebfffffe          BL       MMU_InvalidateTLB
;;;42     
;;;43         /*SROM*/
;;;44         //MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
;;;45         MMU_SetMTT(0x00000000,0x03f00000,0x00000000,RW_CNB);   //SROM Bank0
0000a0  e59f316c          LDR      r3,|L1.532|
0000a4  e3a02000          MOV      r2,#0
0000a8  e3a017fc          MOV      r1,#0x3f00000
0000ac  e3a00000          MOV      r0,#0
0000b0  ebfffffe          BL       MMU_SetMTT
;;;46         MMU_SetMTT(0x04000000,0x07f00000,0x04000000,RW_NCNB);  //SROM Bank1
0000b4  e59f315c          LDR      r3,|L1.536|
0000b8  e3a02640          MOV      r2,#0x4000000
0000bc  e3a0167f          MOV      r1,#0x7f00000
0000c0  e3a00640          MOV      r0,#0x4000000
0000c4  ebfffffe          BL       MMU_SetMTT
;;;47         MMU_SetMTT(0x08000000,0x0bf00000,0x08000000,RW_CNB);   //SROM Bank2
0000c8  e59f3144          LDR      r3,|L1.532|
0000cc  e3a02680          MOV      r2,#0x8000000
0000d0  e3a016bf          MOV      r1,#0xbf00000
0000d4  e3a00680          MOV      r0,#0x8000000
0000d8  ebfffffe          BL       MMU_SetMTT
;;;48         //MMU_SetMTT(0x0c000000,0x0c000000,0x0c000000,RW_NCNB);  //Stepping Stone 4KB
;;;49     
;;;50         /*Normal SDRAM*/    
;;;51         MMU_SetMTT(0x10000000,0x10f00000,0x10000000,RW_CB);    //SDRAM System Group S0-1
0000dc  e59f3138          LDR      r3,|L1.540|
0000e0  e3a02540          MOV      r2,#0x10000000
0000e4  e28218f0          ADD      r1,r2,#0xf00000
0000e8  e3a00540          MOV      r0,#0x10000000
0000ec  ebfffffe          BL       MMU_SetMTT
;;;52         MMU_SetMTT(0x11000000,0x13e00000,0x11000000,RW_NCNB);  //SDRAM System Group S0-2
0000f0  e59f3120          LDR      r3,|L1.536|
0000f4  e3a02544          MOV      r2,#0x11000000
0000f8  e28217b8          ADD      r1,r2,#0x2e00000
0000fc  e3a00544          MOV      r0,#0x11000000
000100  ebfffffe          BL       MMU_SetMTT
;;;53         MMU_SetMTT(0x13f00000,0x13f00000,0x13f00000,RW_CB);    //SDRAM System Group S0-3
000104  e59f3110          LDR      r3,|L1.540|
000108  e59f2110          LDR      r2,|L1.544|
00010c  e1a01002          MOV      r1,r2
000110  e1a00002          MOV      r0,r2
000114  ebfffffe          BL       MMU_SetMTT
;;;54     
;;;55         /*Mobile SDRAM*/    
;;;56         MMU_SetMTT(0x20000000,0x21f00000,0x20000000,RW_NCNB);  //SDRAM Image Subsystem Group I0
000118  e59f30f8          LDR      r3,|L1.536|
00011c  e3a02580          MOV      r2,#0x20000000
000120  e282177c          ADD      r1,r2,#0x1f00000
000124  e3a00580          MOV      r0,#0x20000000
000128  ebfffffe          BL       MMU_SetMTT
;;;57     
;;;58         /*SFR & Etc*/    
;;;59         MMU_SetMTT(0x40000000,0x4a100000,0x40000000,RW_NCNB);  //SFR
00012c  e59f30e4          LDR      r3,|L1.536|
000130  e3a02440          MOV      r2,#0x40000000
000134  e28216a1          ADD      r1,r2,#0xa100000
000138  e3a00440          MOV      r0,#0x40000000
00013c  ebfffffe          BL       MMU_SetMTT
;;;60         //MMU_SetMTT(0x4a200000,0xfff00000,0x4a200000,RW_FAULT); //not used
;;;61     
;;;62         MMU_SetTTBase(_MMUTT_STARTADDRESS);
000140  e59f00c8          LDR      r0,|L1.528|
000144  ebfffffe          BL       MMU_SetTTBase
;;;63         MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); 
000148  e59f00d4          LDR      r0,|L1.548|
00014c  ebfffffe          BL       MMU_SetDomain
;;;64         	//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
;;;65     
;;;66         MMU_SetProcessId(0x0);
000150  e3a00000          MOV      r0,#0
000154  ebfffffe          BL       MMU_SetProcessId
;;;67         MMU_EnableAlignFault();
000158  ebfffffe          BL       MMU_EnableAlignFault
;;;68     
;;;69         MMU_EnableMIDCache();
00015c  ebfffffe          BL       MMU_EnableMIDCache
;;;70     
;;;71     
;;;72     //Test M&I&D En=========================================
;;;73     /*
;;;74         MMU_EnableMMU();
;;;75         MMU_EnableICache();
;;;76         MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.    
;;;77     */
;;;78     //===================================================
;;;79     
;;;80     }    
000160  e8bd8038          LDMFD    sp!,{r3-r5,pc}
                          ENDP

                  ChangeRomCacheStatus PROC
;;;84     void ChangeRomCacheStatus(int attr)
;;;85     {
000164  e92d4070          STMFD    sp!,{r4-r6,lr}
000168  e1a06000          MOV      r6,r0
;;;86         int i,j;
;;;87         MMU_DisableDCache();
00016c  ebfffffe          BL       MMU_DisableDCache
;;;88         MMU_DisableICache();
000170  ebfffffe          BL       MMU_DisableICache
;;;89         //If write-back is used,the DCache should be cleared.
;;;90         for(i=0;i<4;i++)
000174  e3a05000          MOV      r5,#0
                  |L1.376|
000178  e3550004          CMP      r5,#4
00017c  aa00000d          BGE      |L1.440|
000180  ea000001          B        |L1.396|
                  |L1.388|
000184  e2855001          ADD      r5,r5,#1
000188  eafffffa          B        |L1.376|
;;;91         	for(j=0;j<128;j++)
                  |L1.396|
00018c  e3a04000          MOV      r4,#0
                  |L1.400|
000190  e3540080          CMP      r4,#0x80
000194  aa000006          BGE      |L1.436|
000198  ea000001          B        |L1.420|
                  |L1.412|
00019c  e2844001          ADD      r4,r4,#1
0001a0  eafffffa          B        |L1.400|
;;;92         	    MMU_CleanInvalidateDCacheSET((i<<30)|(j<<5));
                  |L1.420|
0001a4  e1a01f05          MOV      r1,r5,LSL #30
0001a8  e1810284          ORR      r0,r1,r4,LSL #5
0001ac  ebfffffe          BL       MMU_CleanInvalidateDCacheSET
0001b0  eafffff9          B        |L1.412|
                  |L1.436|
0001b4  eafffff2          B        |L1.388|
;;;93         MMU_InvalidateICache();
                  |L1.440|
0001b8  ebfffffe          BL       MMU_InvalidateICache
;;;94         MMU_DisableMMU();
0001bc  ebfffffe          BL       MMU_DisableMMU
;;;95         MMU_InvalidateTLB();
0001c0  ebfffffe          BL       MMU_InvalidateTLB
;;;96     
;;;97         MMU_SetMTT(0x00000000,0x03f00000,0x00000000,attr);   //SROM Bank0
0001c4  e1a03006          MOV      r3,r6
0001c8  e3a02000          MOV      r2,#0
0001cc  e3a017fc          MOV      r1,#0x3f00000
0001d0  e3a00000          MOV      r0,#0
0001d4  ebfffffe          BL       MMU_SetMTT
;;;98         MMU_SetMTT(0x04000000,0x07f00000,0x04000000,attr);  //SROM Bank1
0001d8  e1a03006          MOV      r3,r6
0001dc  e3a02640          MOV      r2,#0x4000000
0001e0  e3a0167f          MOV      r1,#0x7f00000
0001e4  e3a00640          MOV      r0,#0x4000000
0001e8  ebfffffe          BL       MMU_SetMTT
;;;99         MMU_SetMTT(0x08000000,0x0bf00000,0x08000000,attr);   //SROM Bank2
0001ec  e1a03006          MOV      r3,r6
0001f0  e3a02680          MOV      r2,#0x8000000
0001f4  e3a016bf          MOV      r1,#0xbf00000
0001f8  e3a00680          MOV      r0,#0x8000000
0001fc  ebfffffe          BL       MMU_SetMTT
;;;100    
;;;101        MMU_EnableMMU();
000200  ebfffffe          BL       MMU_EnableMMU
;;;102        MMU_EnableICache();
000204  ebfffffe          BL       MMU_EnableICache
;;;103        MMU_EnableDCache();
000208  ebfffffe          BL       MMU_EnableDCache
;;;104    }    
00020c  e8bd8070          LDMFD    sp!,{r4-r6,pc}
                  |L1.528|
000210  13ff8000          DCD      0x13ff8000
                  |L1.532|
000214  00000c1a          DCD      0x00000c1a
                  |L1.536|
000218  00000c12          DCD      0x00000c12
                  |L1.540|
00021c  00000c1e          DCD      0x00000c1e
                  |L1.544|
000220  13f00000          DCD      0x13f00000
                  |L1.548|
000224  55555551          DCD      0x55555551
                          ENDP



        END

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