📄 memtest.txt
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; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-errors .\err\memtest.err -O0 -asm -g+ -cpu 5TEJ -fs -Wd -Ec -I.\include "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
Ch3_SRAM_CONTROLLER PROC
;;;21 void Ch3_SRAM_CONTROLLER(int Print_msg)
;;;22 {
|L1.0|
000000 e92d47f0 STMFD sp!,{r4-r10,lr}
000004 e1a05000 MOV r5,r0
;;;23 U32 addr=0, indata, src_data, i;
000008 e3a04000 MOV r4,#0
;;;24 U32 error;
;;;25 static int offset=0;
;;;26 U16 jump_offset=1;
00000c e3a07001 MOV r7,#1
;;;27
;;;28
;;;29 //Uart_Printf("Check: SRAM Area must be in non-cacheable area!\n");
;;;30 //Uart_Printf("SRAM W/R test[%xh-%xh], R/W offset[%d]\n", SRAM_SADDR, SRAM_EADDR-1, offset);
;;;31 // for(i=0; i<3; i++) { // 8/16/32-bit.
;;;32 for(i=2; i<3; i++) { // 8/16/32-bit.
000010 e3a08002 MOV r8,#2
|L1.20|
000014 e3580003 CMP r8,#3
000018 2a0000a4 BCS |L1.688|
00001c ea000001 B |L1.40|
|L1.32|
000020 e2888001 ADD r8,r8,#1
000024 eafffffa B |L1.20|
;;;33
;;;34 if(i==0) jump_offset=1;
|L1.40|
000028 e3580000 CMP r8,#0
00002c 1a000001 BNE |L1.56|
000030 e3a07001 MOV r7,#1
000034 ea000006 B |L1.84|
;;;35 else if(i==1) jump_offset=2;
|L1.56|
000038 e3580001 CMP r8,#1
00003c 1a000001 BNE |L1.72|
000040 e3a07002 MOV r7,#2
000044 ea000002 B |L1.84|
;;;36 else if(i==2) jump_offset=4;
|L1.72|
000048 e3580002 CMP r8,#2
00004c 1a000000 BNE |L1.84|
000050 e3a07004 MOV r7,#4
;;;37
;;;38 ///////////////////// Clear Source/Target ////////////////////
;;;39 //Uart_Printf("Clear data.\n");
;;;40 for(addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=4) {
|L1.84|
000054 e3a04000 MOV r4,#0
|L1.88|
000058 e2840544 ADD r0,r4,#0x11000000
00005c e290c4ef ADDS r12,r0,#0xef000000
000060 225ccb80 SUBCSS r12,r12,#0x20000
000064 2a000007 BCS |L1.136|
000068 ea000001 B |L1.116|
|L1.108|
00006c e2844004 ADD r4,r4,#4
000070 eafffff8 B |L1.88|
;;;41 *(U32 *)(SRAM_SADDR+addr) = 0x0;
|L1.116|
000074 e3a00000 MOV r0,#0
000078 e3a01544 MOV r1,#0x11000000
00007c e7810004 STR r0,[r1,r4]
;;;42 if(!(addr%(4*1024))) {
000080 e1a00000 NOP
;;;43 //Uart_Printf("\b\b\b\b\b\b\b\b\b\b%10x", SRAM_SADDR+addr);
;;;44 }
;;;45 }
000084 eafffff8 B |L1.108|
;;;46 //Uart_Printf("\b\b\b\b\b\b\b\b\b\b%10x\n", SRAM_SADDR+addr);
;;;47
;;;48 ///////////////////// Write ////////////////////
;;;49 //Uart_Printf("Write data[%x-%x].\n", SRAM_SADDR, SRAM_EADDR);
;;;50 if(Print_msg) Uart_Printf("%d-bit data write.", jump_offset*8);
|L1.136|
000088 e3550000 CMP r5,#0
00008c 0a000002 BEQ |L1.156|
000090 e1a01187 MOV r1,r7,LSL #3
000094 e28f0f8b ADR r0,|L1.712|
000098 ebfffffe BL _printf
;;;51 if(Print_msg) Uart_Printf("ADDR:%8x", SRAM_SADDR);
|L1.156|
00009c e3550000 CMP r5,#0
0000a0 0a000002 BEQ |L1.176|
0000a4 e3a01544 MOV r1,#0x11000000
0000a8 e28f0f8b ADR r0,|L1.732|
0000ac ebfffffe BL _printf
;;;52 Led_Display(0x1);
|L1.176|
0000b0 e3a00001 MOV r0,#1
0000b4 ebfffffe BL Led_Display
;;;53 for(addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=jump_offset) {
0000b8 e3a04000 MOV r4,#0
|L1.188|
0000bc e2840544 ADD r0,r4,#0x11000000
0000c0 e290c4ef ADDS r12,r0,#0xef000000
0000c4 225ccb80 SUBCSS r12,r12,#0x20000
0000c8 2a00001e BCS |L1.328|
0000cc ea000001 B |L1.216|
|L1.208|
0000d0 e0844007 ADD r4,r4,r7
0000d4 eafffff8 B |L1.188|
;;;54
;;;55 src_data = addr+offset;
|L1.216|
0000d8 e59f0208 LDR r0,|L1.744|
0000dc e5900000 LDR r0,[r0,#0] ; offset@Ch3_SRAM_CONTROLLER_0
0000e0 e0846000 ADD r6,r4,r0
;;;56
;;;57 switch(jump_offset) {
0000e4 e3570001 CMP r7,#1
0000e8 0a000004 BEQ |L1.256|
0000ec e3570002 CMP r7,#2
0000f0 0a000005 BEQ |L1.268|
0000f4 e3570004 CMP r7,#4
0000f8 1a000009 BNE |L1.292|
0000fc ea000005 B |L1.280|
;;;58 case 1:
;;;59 *(U8 *)(SRAM_SADDR+addr) = src_data;
|L1.256|
000100 e3a00544 MOV r0,#0x11000000
000104 e7c06004 STRB r6,[r0,r4]
;;;60 break;
000108 ea000005 B |L1.292|
;;;61 case 2:
;;;62 *(U16 *)(SRAM_SADDR+addr) = src_data;
|L1.268|
00010c e3a00544 MOV r0,#0x11000000
000110 e18060b4 STRH r6,[r0,r4]
;;;63 break;
000114 ea000002 B |L1.292|
;;;64 case 4:
;;;65 *(U32 *)(SRAM_SADDR+addr) = src_data;
|L1.280|
000118 e3a00544 MOV r0,#0x11000000
00011c e7806004 STR r6,[r0,r4]
;;;66 break;
000120 e1a00000 NOP
;;;67 }
;;;68 if(!(addr%(4*1024))) {
|L1.292|
000124 e1a00a04 MOV r0,r4,LSL #20
000128 e1b00a20 MOVS r0,r0,LSR #20
00012c 1a000004 BNE |L1.324|
;;;69 if(Print_msg) Uart_Printf("\b\b\b\b\b\b\b\b%8x", SRAM_SADDR+addr);
000130 e3550000 CMP r5,#0
000134 0a000002 BEQ |L1.324|
000138 e2841544 ADD r1,r4,#0x11000000
00013c e28f0f6a ADR r0,|L1.748|
000140 ebfffffe BL _printf
;;;70 }
;;;71 }
|L1.324|
000144 eaffffe1 B |L1.208|
;;;72 if(Print_msg) Uart_Printf("\b\b\b\b\b\b\b\b%8x ", SRAM_SADDR+addr);
|L1.328|
000148 e3550000 CMP r5,#0
00014c 0a000002 BEQ |L1.348|
000150 e2841544 ADD r1,r4,#0x11000000
000154 e28f0f67 ADR r0,|L1.760|
000158 ebfffffe BL _printf
;;;73
;;;74 ///////////////////// Verify //////////////////////
;;;75 //Uart_Printf("Verify[%x-%x].\n", SRAM_SADDR, SRAM_EADDR);
;;;76 if(Print_msg) Uart_Printf("Verify...");
|L1.348|
00015c e3550000 CMP r5,#0
000160 0a000001 BEQ |L1.364|
000164 e28f0f67 ADR r0,|L1.776|
000168 ebfffffe BL _printf
;;;77 if(Print_msg) Uart_Printf("ADDR:%8x", SRAM_SADDR);
|L1.364|
00016c e3550000 CMP r5,#0
000170 0a000002 BEQ |L1.384|
000174 e3a01544 MOV r1,#0x11000000
000178 e28f0f57 ADR r0,|L1.732|
00017c ebfffffe BL _printf
;;;78 Led_Display(0x2);
|L1.384|
000180 e3a00002 MOV r0,#2
000184 ebfffffe BL Led_Display
;;;79 for(error=0, addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=jump_offset) {
000188 e3a0a000 MOV r10,#0
00018c e3a04000 MOV r4,#0
|L1.400|
000190 e2840544 ADD r0,r4,#0x11000000
000194 e290c4ef ADDS r12,r0,#0xef000000
000198 225ccb80 SUBCSS r12,r12,#0x20000
00019c 2a00002f BCS |L1.608|
0001a0 ea000001 B |L1.428|
|L1.420|
0001a4 e0844007 ADD r4,r4,r7
0001a8 eafffff8 B |L1.400|
;;;80 switch(jump_offset) {
|L1.428|
0001ac e3570001 CMP r7,#1
0001b0 0a000004 BEQ |L1.456|
0001b4 e3570002 CMP r7,#2
0001b8 0a000009 BEQ |L1.484|
0001bc e3570004 CMP r7,#4
0001c0 1a000015 BNE |L1.540|
0001c4 ea00000e B |L1.516|
;;;81 case 1:
;;;82 src_data = (U8)(addr+offset);
|L1.456|
0001c8 e59f0118 LDR r0,|L1.744|
0001cc e5900000 LDR r0,[r0,#0] ; offset@Ch3_SRAM_CONTROLLER_0
0001d0 e0840000 ADD r0,r4,r0
0001d4 e20060ff AND r6,r0,#0xff
;;;83 indata = *(U8 *)(SRAM_SADDR+addr);
0001d8 e3a00544 MOV r0,#0x11000000
0001dc e7d09004 LDRB r9,[r0,r4]
;;;84 break;
0001e0 ea00000d B |L1.540|
;;;85 case 2:
;;;86 src_data = (U16)(addr+offset);
|L1.484|
0001e4 e59f00fc LDR r0,|L1.744|
0001e8 e5900000 LDR r0,[r0,#0] ; offset@Ch3_SRAM_CONTROLLER_0
0001ec e0840000 ADD r0,r4,r0
0001f0 e1a06800 MOV r6,r0,LSL #16
0001f4 e1a06826 MOV r6,r6,LSR #16
;;;87 indata = *(U16 *)(SRAM_SADDR+addr);
0001f8 e3a00544 MOV r0,#0x11000000
0001fc e19090b4 LDRH r9,[r0,r4]
;;;88 break;
000200 ea000005 B |L1.540|
;;;89 case 4:
;;;90 src_data = (U32)(addr+offset);
|L1.516|
000204 e59f00dc LDR r0,|L1.744|
000208 e5900000 LDR r0,[r0,#0] ; offset@Ch3_SRAM_CONTROLLER_0
00020c e0846000 ADD r6,r4,r0
;;;91 indata = *(U32 *)(SRAM_SADDR+addr);
000210 e3a00544 MOV r0,#0x11000000
000214 e7909004 LDR r9,[r0,r4]
;;;92 break;
000218 e1a00000 NOP
;;;93 }
;;;94
;;;95 if(!(addr%(4*1024))) {
|L1.540|
00021c e1a00a04 MOV r0,r4,LSL #20
000220 e1b00a20 MOVS r0,r0,LSR #20
000224 1a000004 BNE |L1.572|
;;;96 if(Print_msg) Uart_Printf("\b\b\b\b\b\b\b\b%8x", SRAM_SADDR+addr);
000228 e3550000 CMP r5,#0
00022c 0a000002 BEQ |L1.572|
000230 e2841544 ADD r1,r4,#0x11000000
000234 e28f00b0 ADR r0,|L1.748|
000238 ebfffffe BL _printf
;;;97 }
;;;98
;;;99 if(indata != src_data) {
|L1.572|
00023c e1590006 CMP r9,r6
000240 0a000005 BEQ |L1.604|
;;;100 error++;
000244 e28aa001 ADD r10,r10,#1
;;;101 Uart_Printf("\n\n%xH[W:%x, R:%x]\n", addr, src_data, indata);
000248 e1a03009 MOV r3,r9
00024c e1a02006 MOV r2,r6
000250 e1a01004 MOV r1,r4
000254 e28f00b8 ADR r0,|L1.788|
000258 ebfffffe BL _printf
;;;102 }
;;;103 }
|L1.604|
00025c eaffffd0 B |L1.420|
;;;104 if(Print_msg) Uart_Printf("\b\b\b\b\b\b\b\b%8x ", SRAM_SADDR+addr);
|L1.608|
000260 e3550000 CMP r5,#0
000264 0a000002 BEQ |L1.628|
000268 e2841544 ADD r1,r4,#0x11000000
00026c e28f0084 ADR r0,|L1.760|
000270 ebfffffe BL _printf
;;;105
;;;106 if(error!=0) {
|L1.628|
000274 e35a0000 CMP r10,#0
000278 0a000005 BEQ |L1.660|
;;;107 if(Print_msg) Uart_Printf("ERROR(%d)...\n\n", error);
00027c e3550000 CMP r5,#0
000280 0a000007 BEQ |L1.676|
000284 e1a0100a MOV r1,r10
000288 e28f0098 ADR r0,|L1.808|
00028c ebfffffe BL _printf
000290 ea000003 B |L1.676|
;;;108 } else {
;;;109 if(Print_msg) Uart_Printf("OK!\n");
|L1.660|
000294 e3550000 CMP r5,#0
000298 0a000001 BEQ |L1.676|
00029c e28f0094 ADR r0,|L1.824|
0002a0 ebfffffe BL _printf
;;;110 //Uart_Printf(".");
;;;111 }
;;;112 Led_Display(0xf);
|L1.676|
0002a4 e3a0000f MOV r0,#0xf
0002a8 ebfffffe BL Led_Display
;;;113 }
0002ac eaffff5b B |L1.32|
;;;114
;;;115 offset++;
|L1.688|
0002b0 e59f0030 LDR r0,|L1.744|
0002b4 e5900000 LDR r0,[r0,#0] ; offset@Ch3_SRAM_CONTROLLER_0
0002b8 e2800001 ADD r0,r0,#1
0002bc e59f1024 LDR r1,|L1.744|
0002c0 e5810000 STR r0,[r1,#0] ; offset@Ch3_SRAM_CONTROLLER_0
;;;116 }
0002c4 e8bd87f0 LDMFD sp!,{r4-r10,pc}
|L1.712|
0002c8 622d6425 DCB "%d-b"
0002cc 64207469 DCB "it d"
0002d0 20617461 DCB "ata "
0002d4 74697277 DCB "writ"
0002d8 00002e65 DCB "e.\0\0"
|L1.732|
0002dc 52444441 DCB "ADDR"
0002e0 7838253a DCB ":%8x"
0002e4 00000000 DCB "\0\0\0\0"
|L1.744|
0002e8 00000000 DCD ||.bss$2||
|L1.748|
0002ec 08080808 DCB "\b\b\b\b"
0002f0 08080808 DCB "\b\b\b\b"
0002f4 00783825 DCB "%8x\0"
|L1.760|
0002f8 08080808 DCB "\b\b\b\b"
0002fc 08080808 DCB "\b\b\b\b"
000300 20783825 DCB "%8x "
000304 00000020 DCB " \0\0\0"
|L1.776|
000308 69726556 DCB "Veri"
00030c 2e2e7966 DCB "fy.."
000310 0000002e DCB ".\0\0\0"
|L1.788|
000314 78250a0a DCB "\n\n%x"
000318 3a575b48 DCB "H[W:"
00031c 202c7825 DCB "%x, "
000320 78253a52 DCB "R:%x"
000324 00000a5d DCB "]\n\0\0"
|L1.808|
000328 4f525245 DCB "ERRO"
00032c 64252852 DCB "R(%d"
000330 2e2e2e29 DCB ")..."
000334 00000a0a DCB "\n\n\0\0"
|L1.824|
000338 0a214b4f DCB "OK!\n"
00033c 00000000 DCB "\0\0\0\0"
ENDP
AREA ||.bss||, NOINIT, ALIGN=2
||offset@Ch3_SRAM_CONTROLLER_0||
||.bss$2||
% 4
END
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