📄 sleep.txt
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;;;404
;;;405 //SoftReset Ready
;;;406 else
;;;407 {
;;;408 Uart_Printf("[SoftReset Test]\n");
|L1.2984|
000ba8 e28f002c ADR r0,|L1.3036|
000bac ebfffffe BL _printf
;;;409
;;;410 #if CHECK_SDRAM_SELFREFRESH
;;;411 Test_InitSDRAM(_NONCACHE_STARTADDRESS,0x400000); //Write test data into NONCACHEABLE AREA
000bb0 e3a01840 MOV r1,#0x400000
000bb4 e3a00544 MOV r0,#0x11000000
000bb8 ebfffffe BL Test_InitSDRAM
;;;412 #endif
;;;413
;;;414 //SRAMKey_Run = xxx;// Change if you want..
;;;415
;;;416 //SoftReset
;;;417 Uart_Printf("Now, Soft Reset causes reset on S3C24A0 except SDRAM. \n");
000bbc e28f004c ADR r0,|L1.3088|
000bc0 ebfffffe BL _printf
;;;418 Uart_TxEmpty(0); //Wait until UART0 Tx buffer empty.
000bc4 e3a00000 MOV r0,#0
000bc8 ebfffffe BL Uart_TxEmpty
;;;419 rSOFTRESET=0xa3; //Software Reset
000bcc e3a000a3 MOV r0,#0xa3
000bd0 e3a01440 MOV r1,#0x40000000
000bd4 e5810038 STR r0,[r1,#0x38]
;;;420 }
;;;421 }
|L1.3032|
000bd8 e8bd8008 LDMFD sp!,{r3,pc}
|L1.3036|
000bdc 666f535b DCB "[Sof"
000be0 73655274 DCB "tRes"
000be4 54207465 DCB "et T"
000be8 5d747365 DCB "est]"
000bec 0000000a DCB "\n\0\0\0"
|L1.3056|
000bf0 6f535b0a DCB "\n[So"
000bf4 65527466 DCB "ftRe"
000bf8 5d746573 DCB "set]"
000bfc 73655420 DCB " Tes"
000c00 73692074 DCB "t is"
000c04 6e6f4420 DCB " Don"
000c08 21212165 DCB "e!!!"
000c0c 0000000a DCB "\n\0\0\0"
|L1.3088|
000c10 2c776f4e DCB "Now,"
000c14 666f5320 DCB " Sof"
000c18 65522074 DCB "t Re"
000c1c 20746573 DCB "set "
000c20 73756163 DCB "caus"
000c24 72207365 DCB "es r"
000c28 74657365 DCB "eset"
000c2c 206e6f20 DCB " on "
000c30 32433353 DCB "S3C2"
000c34 20304134 DCB "4A0 "
000c38 65637865 DCB "exce"
000c3c 53207470 DCB "pt S"
000c40 4d415244 DCB "DRAM"
000c44 000a202e DCB ". \n\0"
ENDP
Test_WDTReset PROC
;;;423 void Test_WDTReset(void)
;;;424 {
000c48 e92d4008 STMFD sp!,{r3,lr}
;;;425 //Return from WarmReset
;;;426 if(rALIVECON & 1<<5)
000c4c e51f0ba8 LDR r0,|L1.172|
000c50 e5900044 LDR r0,[r0,#0x44]
000c54 e3100020 TST r0,#0x20
000c58 0a000008 BEQ |L1.3200|
;;;427 {
;;;428 Uart_Printf("[Watch-dog Reset Test]\n");
000c5c e28f007c ADR r0,|L1.3296|
000c60 ebfffffe BL _printf
;;;429
;;;430 #if CHECK_SDRAM_SELFREFRESH
;;;431 Test_CheckSDRAM(_NONCACHE_STARTADDRESS,0x400000); //Check NONCACHEABLE AREA
000c64 e3a01840 MOV r1,#0x400000
000c68 e3a00544 MOV r0,#0x11000000
000c6c ebfffffe BL Test_CheckSDRAM
;;;432 #endif
;;;433
;;;434 Clear_SleepKey();
000c70 ebfffffe BL Clear_SleepKey
;;;435 Uart_Printf("\n[Watch-dog Reset] Test is Done!!!\n");
000c74 e28f007c ADR r0,|L1.3320|
000c78 ebfffffe BL _printf
000c7c ea000016 B |L1.3292|
;;;436 }
;;;437
;;;438 //WarmReset Ready
;;;439 else
;;;440 {
;;;441 Uart_Printf("[Watch-dog Reset Test]\n");
|L1.3200|
000c80 e28f0058 ADR r0,|L1.3296|
000c84 ebfffffe BL _printf
;;;442
;;;443 #if CHECK_SDRAM_SELFREFRESH
;;;444 Test_InitSDRAM(_NONCACHE_STARTADDRESS,0x400000); //Write test data into NONCACHEABLE AREA
000c88 e3a01840 MOV r1,#0x400000
000c8c e3a00544 MOV r0,#0x11000000
000c90 ebfffffe BL Test_InitSDRAM
;;;445 #endif
;;;446
;;;447 rWTCON = 0; // clear wtcon
000c94 e3a00000 MOV r0,#0
000c98 e59f107c LDR r1,|L1.3356|
000c9c e5810000 STR r0,[r1,#0]
;;;448 rWTDAT = 8448 ; // WDT clock = 128/1M --> 128us*8448 = 1s
000ca0 e3a00d84 MOV r0,#0x2100
000ca4 e1c11000 BIC r1,r1,r0
000ca8 e5810004 STR r0,[r1,#4]
;;;449 rWTCNT = 8448 ;
000cac e3a00d84 MOV r0,#0x2100
000cb0 e1c11000 BIC r1,r1,r0
000cb4 e5810008 STR r0,[r1,#8]
;;;450
;;;451 //SRAMKey_Run = xxx;// Change if you want..
;;;452
;;;453 // WDT reset enable
;;;454 Uart_Printf("After 1 sec the WDT reset will be assered. ..\n");
000cb8 e28f0060 ADR r0,|L1.3360|
000cbc ebfffffe BL _printf
;;;455 Uart_TxEmpty(0);
000cc0 e3a00000 MOV r0,#0
000cc4 ebfffffe BL Uart_TxEmpty
;;;456 rWTCON = ((PCLK/1000000-1)<<8) |( 1<<5) | (3<<3) | (1);
000cc8 e59f0080 LDR r0,|L1.3408|
000ccc e59f1048 LDR r1,|L1.3356|
000cd0 e5810000 STR r0,[r1,#0]
;;;457 while(1);
000cd4 e1a00000 NOP
|L1.3288|
000cd8 eafffffe B |L1.3288|
;;;458 }
;;;459 }
|L1.3292|
000cdc e8bd8008 LDMFD sp!,{r3,pc}
|L1.3296|
000ce0 7461575b DCB "[Wat"
000ce4 642d6863 DCB "ch-d"
000ce8 5220676f DCB "og R"
000cec 74657365 DCB "eset"
000cf0 73655420 DCB " Tes"
000cf4 000a5d74 DCB "t]\n\0"
|L1.3320|
000cf8 61575b0a DCB "\n[Wa"
000cfc 2d686374 DCB "tch-"
000d00 20676f64 DCB "dog "
000d04 65736552 DCB "Rese"
000d08 54205d74 DCB "t] T"
000d0c 20747365 DCB "est "
000d10 44207369 DCB "is D"
000d14 21656e6f DCB "one!"
000d18 000a2121 DCB "!!\n\0"
|L1.3356|
000d1c 44100000 DCD 0x44100000
|L1.3360|
000d20 65746641 DCB "Afte"
000d24 20312072 DCB "r 1 "
000d28 20636573 DCB "sec "
000d2c 20656874 DCB "the "
000d30 20544457 DCB "WDT "
000d34 65736572 DCB "rese"
000d38 69772074 DCB "t wi"
000d3c 62206c6c DCB "ll b"
000d40 73612065 DCB "e as"
000d44 65726573 DCB "sere"
000d48 2e202e64 DCB "d. ."
000d4c 00000a2e DCB ".\n\0\0"
|L1.3408|
000d50 00003239 DCD 0x00003239
ENDP
Test_BattFault PROC
;;;462 void Test_BattFault(void)
;;;463 {
000d54 e92d4008 STMFD sp!,{r3,lr}
;;;464 //Return from BATT_FLT
;;;465 if(rALIVECON & 1<<7)
000d58 e51f0cb4 LDR r0,|L1.172|
000d5c e5900044 LDR r0,[r0,#0x44]
000d60 e3100080 TST r0,#0x80
000d64 0a000026 BEQ |L1.3588|
;;;466 {
;;;467 Uart_Printf("[nBATT_FAULT signal Test]\n");
000d68 e28f0fab ADR r0,|L1.4124|
000d6c ebfffffe BL _printf
;;;468
;;;469 #if CHECK_SDRAM_SELFREFRESH
;;;470 Test_CheckSDRAM(_NONCACHE_STARTADDRESS,0x400000); //Check NONCACHEABLE AREA
000d70 e3a01840 MOV r1,#0x400000
000d74 e3a00544 MOV r0,#0x11000000
000d78 ebfffffe BL Test_CheckSDRAM
;;;471 #endif
;;;472
;;;473 #if 1
;;;474 //Unmask interrupt
;;;475 rINTMSK=rINTMSK&~(BIT_EINT11_14); //Just to test
000d7c e51f0c74 LDR r0,|L1.272|
000d80 e5900008 LDR r0,[r0,#8]
000d84 e3c00008 BIC r0,r0,#8
000d88 e51f1c80 LDR r1,|L1.272|
000d8c e5810008 STR r0,[r1,#8]
;;;476 rINTMSK=rINTMSK&~(BIT_EINT7_10); //Just to test
000d90 e1a00001 MOV r0,r1
000d94 e5900008 LDR r0,[r0,#8]
000d98 e3c00004 BIC r0,r0,#4
000d9c e5810008 STR r0,[r1,#8]
;;;477 rINTMSK=rINTMSK&~(BIT_EINT0_2);
000da0 e1a00001 MOV r0,r1
000da4 e5900008 LDR r0,[r0,#8]
000da8 e3c00001 BIC r0,r0,#1
000dac e5810008 STR r0,[r1,#8]
;;;478
;;;479 //Unmask sub interrupt
;;;480 rEINTMASK=rEINTMASK&~(BIT_EINTPEND_EINT0);
000db0 e2810646 ADD r0,r1,#0x4600000
000db4 e5900034 LDR r0,[r0,#0x34]
000db8 e3c00001 BIC r0,r0,#1
000dbc e2811646 ADD r1,r1,#0x4600000
000dc0 e5810034 STR r0,[r1,#0x34]
;;;481 rEINTMASK=rEINTMASK&~(BIT_EINTPEND_EINT1);
000dc4 e1a00001 MOV r0,r1
000dc8 e5900034 LDR r0,[r0,#0x34]
000dcc e3c00002 BIC r0,r0,#2
000dd0 e5810034 STR r0,[r1,#0x34]
;;;482 rEINTMASK=rEINTMASK&~(BIT_EINTPEND_EINT9);
000dd4 e1a00001 MOV r0,r1
000dd8 e5900034 LDR r0,[r0,#0x34]
000ddc e3c00f80 BIC r0,r0,#0x200
000de0 e5810034 STR r0,[r1,#0x34]
;;;483 rEINTMASK=rEINTMASK&~(BIT_EINTPEND_EINT11);
000de4 e1a00001 MOV r0,r1
000de8 e5900034 LDR r0,[r0,#0x34]
000dec e3c00e80 BIC r0,r0,#0x800
000df0 e5810034 STR r0,[r1,#0x34]
;;;484 //for(i=0;i<100;i++);
;;;485 #endif
;;;486
;;;487 Clear_SleepKey();
000df4 ebfffffe BL Clear_SleepKey
;;;488 Uart_Printf("[nBATT_FAULT signal Test is done]\n");
000df8 e28f0f8e ADR r0,|L1.4152|
000dfc ebfffffe BL _printf
000e00 ea000084 B |L1.4120|
;;;489 }
;;;490
;;;491 //BAT_FLT Ready
;;;492 else
;;;493 {
;;;494 Uart_Printf("[nBATT_FAULT signal Test]\n");
|L1.3588|
000e04 e28f0f84 ADR r0,|L1.4124|
000e08 ebfffffe BL _printf
;;;495
;;;496 #if CHECK_SDRAM_SELFREFRESH
;;;497 Test_InitSDRAM(_NONCACHE_STARTADDRESS,0x400000); //Write test data into NONCACHEABLE AREA
000e0c e3a01840 MOV r1,#0x400000
000e10 e3a00544 MOV r0,#0x11000000
000e14 ebfffffe BL Test_InitSDRAM
;;;498 #endif
;;;499 ConfigSleepGPIO();
000e18 ebfffffe BL ConfigSleepGPIO
;;;500
;;;501 //Wake-up(EINT0)
;;;502 rGPCON_L=rGPCON_L&~(3<<0)|(2<<0); //GP0=EINT0
000e1c e51f0d78 LDR r0,|L1.172|
000e20 e5900008 LDR r0,[r0,#8]
000e24 e3c00003 BIC r0,r0,#3
000e28 e3800002 ORR r0,r0,#2
000e2c e51f1d88 LDR r1,|L1.172|
000e30 e5810008 STR r0,[r1,#8]
;;;503 rEXTINTC0=rEXTINTC0&~(7<<0)|(2<<0); //EINT0=falling edge triggered
000e34 e1a00001 MOV r0,r1
000e38 e5900018 LDR r0,[r0,#0x18]
000e3c e3c00007 BIC r0,r0,#7
000e40 e3800002 ORR r0,r0,#2
000e44 e5810018 STR r0,[r1,#0x18]
;;;504
;;;505 //Wake-up(EINT1)
;;;506 rGPCON_L=rGPCON_L&~(3<<2)|(2<<2); //GP1=EINT1
000e48 e1a00001 MOV r0,r1
000e4c e5900008 LDR r0,[r0,#8]
000e50 e3c0000c BIC r0,r0,#0xc
000e54 e3800008 ORR r0,r0,#8
000e58 e5810008 STR r0,[r1,#8]
;;;507 rEXTINTC0=rEXTINTC0&~(7<<4)|(2<<4); //EINT1=falling edge triggered
000e5c e1a00001 MOV r0,r1
000e60 e5900018 LDR r0,[r0,#0x18]
000e64 e3c00070 BIC r0,r0,#0x70
000e68 e3800020 ORR r0,r0,#0x20
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