nand_mtd.c

8032底层驱动部分。因为可以移植 所以单独来拿出来

	else		// chip select 1
	{
		cs = 1;
		SET_NFI_CS1;
	}


	if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
	{
		*NFI_PAGEFMT = PAGEFMT_512_8BIT;
	}
   else
   {
		*NFI_PAGEFMT = PAGEFMT_512_16BIT;

		#if ((defined(MT6228)) || (defined(MT6229) ))
			*NFI_GPIO_DATA1 &= 0x0FFF;
			*NFI_GPIO_DATA2 &= 0xF000;
		#endif
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;
	status = NANDSUBDriveData[cs].sub_driver->ProgramPage(D, (PageIndex-NANDSUBDriveData[cs].base_page), Data, Spare, ECCFlag);

	if(cs)
		SET_NFI_CS1_END;

	*NFI_OPCON = 0;
	pdn_nfi(0);


	if( status == FS_DATA_ERROR )
		return FS_DATA_ERROR;
	else
		return FS_NO_ERROR;


} /*  End of ProgramPage_512 */

/*******************************************************************************/

int ReadPage_512 (void * DriveData, DWORD PageIndex, BYTE * Data, BYTE * Spare, BYTE SpareFlag, BYTE ECCFlag)
{
	NAND_FLASH_DRV_DATA * D = DriveData;
	kal_uint8 status, cs;


	pdn_nfi(1);

#ifdef _NAND_FLASH_BOOTING_
	PageIndex += NFB_FLASH_BASE_PAGE;
#endif

	if((PageIndex<NANDSUBDriveData[1].base_page) || (NANDSUBDriveData[1].base_page==0)  )		// chip select 0
	{
		cs = 0;
		SET_NFI_CS0;
	}
	else		// chip select 1
	{
		cs = 1;
		SET_NFI_CS1;
	}


	if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
	{
		*NFI_PAGEFMT = PAGEFMT_512_8BIT;
	}
   else
   {
		*NFI_PAGEFMT = PAGEFMT_512_16BIT;

		#if ((defined(MT6228)) || (defined(MT6229) ))
			*NFI_GPIO_DATA1 &= 0x0FFF;
			*NFI_GPIO_DATA2 &= 0xF000;
		#endif
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;
	status = NANDSUBDriveData[cs].sub_driver->ReadPage(D, (PageIndex-NANDSUBDriveData[cs].base_page), Data, Spare, SpareFlag, ECCFlag);

	if(cs)
		SET_NFI_CS1_END;

	*NFI_OPCON = 0;
	pdn_nfi(0);

        return status;
}	/*  End of ReadPage_512 */


/*******************************************************************************/
int ProgramSpare_512(void * DriveData, DWORD PageIndex, BYTE * Data)
{
	NAND_FLASH_DRV_DATA * D = DriveData;
	kal_uint8 status, cs;


	pdn_nfi(1);


#ifdef _NAND_FLASH_BOOTING_
	PageIndex += NFB_FLASH_BASE_PAGE;
#endif

	if((PageIndex<NANDSUBDriveData[1].base_page) || (NANDSUBDriveData[1].base_page==0) )		// chip select 0
	{
		cs = 0;
		SET_NFI_CS0;
	}
	else		// chip select 1
	{
		cs = 1;
		SET_NFI_CS1;
	}


	if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
	{
		*NFI_PAGEFMT = PAGEFMT_512_8BIT;
	}
   else
   {
		*NFI_PAGEFMT = PAGEFMT_512_16BIT;

		#if ((defined(MT6228)) || (defined(MT6229) ))
			*NFI_GPIO_DATA1 &= 0x0FFF;
			*NFI_GPIO_DATA2 &= 0xF000;
		#endif
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;
	status = NANDSUBDriveData[cs].sub_driver->ProgramSpare(D, (PageIndex-NANDSUBDriveData[cs].base_page), Data);

	if(cs)
		SET_NFI_CS1_END;

	*NFI_OPCON = 0;
	pdn_nfi(0);

	if( status == FS_DATA_ERROR )
		return FS_DATA_ERROR;
	else
		return FS_NO_ERROR;


}	/*  End of ProgramSpare_512 */


/*******************************************************************************/
int ReadSpare_512(void * DriveData, DWORD PageIndex, BYTE * Data)	//need modification
{
	NAND_FLASH_DRV_DATA * D = DriveData;
	kal_uint8 status, cs;


	pdn_nfi(1);


#ifdef _NAND_FLASH_BOOTING_
	PageIndex += NFB_FLASH_BASE_PAGE;
#endif

	if((PageIndex<NANDSUBDriveData[1].base_page) || (NANDSUBDriveData[1].base_page==0) )		// chip select 0
	{
		cs = 0;
		SET_NFI_CS0;
	}
	else		// chip select 1
	{
		cs = 1;
		SET_NFI_CS1;
	}


	if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
	{
		*NFI_PAGEFMT = PAGEFMT_512_8BIT;
	}
   else
   {
		*NFI_PAGEFMT = PAGEFMT_512_16BIT;

		#if ((defined(MT6228)) || (defined(MT6229) ))
			*NFI_GPIO_DATA1 &= 0x0FFF;
			*NFI_GPIO_DATA2 &= 0xF000;
		#endif
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;
	status = NANDSUBDriveData[cs].sub_driver->ReadSpare(D, (PageIndex-NANDSUBDriveData[cs].base_page), Data);

	if(cs)
		SET_NFI_CS1_END;

	*NFI_OPCON = 0;
	pdn_nfi(0);

	if( status == FS_DATA_ERROR )
		return FS_DATA_ERROR;
	else
		return FS_NO_ERROR;


} /*  End of ReadSpare_512 */

#ifdef PAGE_COPY_SUPPORT
int CopyPage_512 (void * DriveData, DWORD SrcPageIndex, DWORD DestPageIndex)
{
	NAND_FLASH_DRV_DATA * D = DriveData;
	kal_uint8 status, cs;

	/* page copy back can be performed only within same plane and with same position attribute, i.e.
	 * even to even or odd to odd.
	 */
	#ifdef _NAND_FLASH_BOOTING_
	if(( (SrcPageIndex+NFB_FLASH_BASE_PAGE) < NANDSUBDriveData[1].base_page) 
	    || (NANDSUBDriveData[1].base_page==0)) // chip select 0
	#else
	if((SrcPageIndex < NANDSUBDriveData[1].base_page) || (NANDSUBDriveData[1].base_page==0)) // chip select 0
	#endif
	{
		cs = 0;
	}
	else
	{
		cs = 1;
	}

	/* In case that one device has copy back support and the other does not under dual NAND condition */
	if( NANDSUBDriveData[cs].sub_driver->CopyPermitted )
	{
	#ifdef _NAND_FLASH_BOOTING_
	if( !NANDSUBDriveData[cs].sub_driver->CopyPermitted(DriveData, SrcPageIndex+NFB_FLASH_BASE_PAGE, DestPageIndex+NFB_FLASH_BASE_PAGE) )
	#else
	if( !NANDSUBDriveData[cs].sub_driver->CopyPermitted(DriveData, SrcPageIndex, DestPageIndex) )
	#endif
		return CopyPage_via_MCU(DriveData, SrcPageIndex, DestPageIndex);
	}
	else
	{
		return CopyPage_via_MCU(DriveData, SrcPageIndex, DestPageIndex);
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;

	/* TODO:
	 * read src page data via NFI to ensure that data content is ECC verified. -- kirk
	 */
	if(NANDSUBDriveData[cs].sub_driver->CopyPage)
	{
		if( MTD_STATUS_CORRECTED != NANDFlashMtd.ReadPage(DriveData, SrcPageIndex, (kal_uint8 *)mtd_buffer, (kal_uint8 *)mtd_spare, 1, ECC_WHOLE) )
		{
			pdn_nfi(1);
			if( 0 == cs ) // chip select 1
			{
				SET_NFI_CS0;
			}
			else // chip select 1
			{
				SET_NFI_CS1;
			}

			if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
			{
				*NFI_PAGEFMT = PAGEFMT_512_8BIT;
			}
			else
			{
				*NFI_PAGEFMT = PAGEFMT_512_16BIT;

				#if ((defined(MT6228)) || (defined(MT6229) ))
					*NFI_GPIO_DATA1 &= 0x0FFF;
					*NFI_GPIO_DATA2 &= 0xF000;
				#endif
			}
			#ifdef _NAND_FLASH_BOOTING_
			status = NANDSUBDriveData[cs].sub_driver->CopyPage(D, (SrcPageIndex+NFB_FLASH_BASE_PAGE-NANDSUBDriveData[cs].base_page), 
			                                                   (DestPageIndex+NFB_FLASH_BASE_PAGE-NANDSUBDriveData[cs].base_page));
			#else
			status = NANDSUBDriveData[cs].sub_driver->CopyPage(D, (SrcPageIndex-NANDSUBDriveData[cs].base_page), 
			                                                   (DestPageIndex-NANDSUBDriveData[cs].base_page));
			#endif
			mtd_copy_counts++;
			
			if(cs)
				SET_NFI_CS1_END;

			*NFI_OPCON = 0;
			pdn_nfi(0);

		}
		else// data has been ECC corrected.
			status = NANDFlashMtd.ProgramPage(DriveData, DestPageIndex, (kal_uint8 *)mtd_buffer, (kal_uint8 *)mtd_spare, ECC_WHOLE);
	}
	else
		EXT_ASSERT(0, (kal_uint32)NANDFlashMtd.CopyPage, (kal_uint32)NANDSUBDriveData[cs].sub_driver->CopyPermitted, 0);//should not happen.

	if( status == FS_DATA_ERROR )
		return FS_DATA_ERROR;
	else
		return FS_NO_ERROR;
} /*  End of CopyPage_512 */
#endif


/*******************************************************************************
 *  MTD functions for 2k page-size
 *******************************************************************************/
int ProgramPage_2K (void * DriveData, DWORD PageIndex, BYTE * Data, BYTE * Spare, BYTE ECCFlag)
{
	NAND_FLASH_DRV_DATA * D = DriveData;
	kal_uint8 status, cs;


	pdn_nfi(1);

#ifdef _NAND_FLASH_BOOTING_
	PageIndex += NFB_FLASH_BASE_PAGE;
#endif

	if((PageIndex < NANDSUBDriveData[1].base_page) || (NANDSUBDriveData[1].base_page==0)  )		// chip select 0
	{
		cs = 0;
		SET_NFI_CS0;
	}
	else		// chip select 1
	{
		cs = 1;
		SET_NFI_CS1;
	}


	if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
	{
		*NFI_PAGEFMT = PAGEFMT_2K_8BIT;
	}
   else
   {
		*NFI_PAGEFMT = PAGEFMT_2K_16BIT;

		#if ((defined(MT6228)) || (defined(MT6229) ))
			*NFI_GPIO_DATA1 &= 0x0FFF;
			*NFI_GPIO_DATA2 &= 0xF000;
		#endif
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;
	status = NANDSUBDriveData[cs].sub_driver->ProgramPage(D, (PageIndex-NANDSUBDriveData[cs].base_page), Data, Spare, ECCFlag);

	if(cs)
		SET_NFI_CS1_END;

	*NFI_OPCON = 0;
	pdn_nfi(0);

	if( status == FS_DATA_ERROR )
		return FS_DATA_ERROR;
	else
		return FS_NO_ERROR;

} /*  End of ProgramPage */



/*******************************************************************************/
int ReadPage_2K (void * DriveData, DWORD PageIndex, BYTE * Data, BYTE * Spare, BYTE SpareFlag, BYTE ECCFlag)
{
	NAND_FLASH_DRV_DATA * D = DriveData;
	kal_uint8 status, cs;


	pdn_nfi(1);


#ifdef _NAND_FLASH_BOOTING_
	PageIndex += NFB_FLASH_BASE_PAGE;
#endif

	if((PageIndex < NANDSUBDriveData[1].base_page) || (NANDSUBDriveData[1].base_page==0)  )		// chip select 0
	{
		cs = 0;
		SET_NFI_CS0;
	}
	else		// chip select 1
	{
		cs = 1;
		SET_NFI_CS1;
	}


	if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
	{
		*NFI_PAGEFMT = PAGEFMT_2K_8BIT;
	}
   else
   {
		*NFI_PAGEFMT = PAGEFMT_2K_16BIT;

		#if ((defined(MT6228)) || (defined(MT6229) ))
			*NFI_GPIO_DATA1 &= 0x0FFF;
			*NFI_GPIO_DATA2 &= 0xF000;
		#endif
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;
	status = NANDSUBDriveData[cs].sub_driver->ReadPage(D, (PageIndex-NANDSUBDriveData[cs].base_page), Data, Spare, SpareFlag, ECCFlag);

	if(cs)
		SET_NFI_CS1_END;

	*NFI_OPCON = 0;
	pdn_nfi(0);

        return status;
}	/*  End of ReadPage_2K */



/*******************************************************************************/
int ProgramSpare_2K(void * DriveData, DWORD PageIndex, BYTE * Data)
{
	NAND_FLASH_DRV_DATA * D = DriveData;
	kal_uint8 status, cs;


	pdn_nfi(1);

#ifdef _NAND_FLASH_BOOTING_
	PageIndex += NFB_FLASH_BASE_PAGE;
#endif

	if((PageIndex < NANDSUBDriveData[1].base_page) || (NANDSUBDriveData[1].base_page==0)  )		// chip select 0
	{
		cs = 0;
		SET_NFI_CS0;
	}
	else		// chip select 1
	{
		cs = 1;
		SET_NFI_CS1;
	}


	if (NANDSUBDriveData[cs].io_width == IO_ACCESS_8BIT)
	{
		*NFI_PAGEFMT = PAGEFMT_2K_8BIT;
	}
   else
   {
		*NFI_PAGEFMT = PAGEFMT_2K_16BIT;

		#if ((defined(MT6228)) || (defined(MT6229) ))
			*NFI_GPIO_DATA1 &= 0x0FFF;
			*NFI_GPIO_DATA2 &= 0xF000;
		#endif
	}

	D->flash_info.address_cycle = NANDSUBDriveData[cs].address_cycle;
	D->flash_info.io_width = NANDSUBDriveData[cs].io_width;
	status = NANDSUBDriveData[cs].sub_driver->ProgramSpare(D, (PageIndex-NANDSUBDriveData[cs].base_page), Data);

	if(cs)
		SET_NFI_CS1_END;

	*NFI_OPCON = 0;
	pdn_nfi(0);

	if( status == FS_DATA_ERROR )
		return FS_DATA_ERROR;
	else