che_hw.h

8032底层驱动部分。因为可以移植 所以单独来拿出来

/*****************************************************************************
*  Copyright Statement:
*  --------------------
*  This software is protected by Copyright and the information contained
*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2005
*
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*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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*****************************************************************************/

/*******************************************************************************
 *
 * Filename:
 * ---------
 * che_hw.h
 *
 * Project:
 * --------
 *   MAUI
 *
 * Description:
 * ------------
 *   Cipher/hash engine hw register definitions.
 *
 * Author:
 * -------
 * -------
 *
 *==============================================================================
 *             HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *------------------------------------------------------------------------------
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 *
 *------------------------------------------------------------------------------
 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *==============================================================================
 *******************************************************************************/
#ifndef CHE_HW_H
#define CHE_HW_H

#define CHE_BASE  0x80170000

#define  CHE_PDN_SET     (0x80000310)
#define  CHE_PDN_CLR     (0x80000320)
#define  CHE_PDN_BIT     0x10
#define  CHE_START       (CHE_BASE+0x0)
#define  CHE_CON         (CHE_BASE+0x4)
#define  CHE_IN0         (CHE_BASE+0x8)
#define  CHE_IN1         (CHE_BASE+0xc)
#define  CHE_IN2         (CHE_BASE+0x10)
#define  CHE_IN3         (CHE_BASE+0x14)
#define  CHE_SDRAT       (CHE_BASE+0x18)
#define  CHE_PCNT        (CHE_BASE+0x1c)     /*RO*/
#define  CHE_STAT        (CHE_BASE+0x20)     /*RO*/
#define  CHE_CDES        (CHE_BASE+0x24)     /*RO*/
#define  CHE_INTSTA      (CHE_BASE+0x28)     /*RC*/
#define  CHE_INTEN       (CHE_BASE+0x2c)     /*RW*/
#define  CHE_BCON        (CHE_BASE+0xc0)
#define  CHE_BSRC        (CHE_BASE+0xc4)
#define  CHE_BSEED       (CHE_BASE+0xc8)
#define  CHE_BENC        (CHE_BASE+0xcc)
#define  CHE_BDEC        (CHE_BASE+0xd0)

/*CHE_START*/
#define  CHE_START_DONE       0x0000
#define  CHE_START_STUD       0x0001
#define  CHE_START_LAST       0x0002
#define  CHE_START_WSTAT      0x0004
#define  CHE_START_RSTAT      0x0008
#define  CHE_START_CLEAR      0x0010
#define  CHE_START_UPDES      0x0020
#define  CHE_START_WKEY       0x0040
#define  CHE_START_RKEY       0x0080
#define  CHE_START_UPIV01     0x0100
#define  CHE_START_UPIV23     0x0200
#define  CHE_START_UPK01      0x0400
#define  CHE_START_UPK23      0x0800
#define  CHE_START_UPK45      0x1000
#define  CHE_START_UPK67      0x2000

/*CHE_CON*/
#define  CHE_CON_ATYPE_MASK         0x0007
#define  CHE_CON_ATYPE_MD5          0x0
#define  CHE_CON_ATYPE_SHA1         0x1
#define  CHE_CON_ATYPE_DES          0x2
#define  CHE_CON_ATYPE_3DES         0x3
#define  CHE_CON_ATYPE_AES_128      0x4
#define  CHE_CON_ATYPE_AES_192      0x5
#define  CHE_CON_ATYPE_AES_256      0x6
#define  CHE_CON_DECIPHER           0x0000
#define  CHE_CON_CIPHER             0x0008
#define  CHE_CON_SMODE_ECB          0x0000
#define  CHE_CON_SMODE_CBC          0x0010
#define  CHE_CON_DKEY1_64BIT        0x0000
#define  CHE_CON_DKEY1_56BIT        0x0020
#define  CHE_CON_DKEY2_64BIT        0x0000
#define  CHE_CON_DKEY2_56BIT        0x0040
#define  CHE_CON_DKEY3_64BIT        0x0000
#define  CHE_CON_DKEY3_56BIT        0x0080

/*CHE_IN0*/
#define  CHE_IN0_MASK         0xffffffff

/*CHE_IN1*/
#define  CHE_IN1_MASK         0xffffffff

/*CHE_IN2*/
#define  CHE_IN2_MASK         0xffffffff

/*CHE_IN3*/
#define  CHE_IN3_MASK         0xffffffff

/*CHE_SDRAT*/
#define  CHE_SDRAT_MASK       0x00ff      /*RW*/

/*CHE_PCNT*/
#define  CHE_PCNT_MASK        0x001f      

/*CHE_STAT*/
#define  CHE_STAT_MASK        0x0007      /*RO*/
#define  CHE_STAT_OK          0x0000      /*RO*/
#define  CHE_STAT_CTRL_ERR    0x0001      /*RO*/
#define  CHE_STAT_ZEROLEN     0x0002      /*RO*/
#define  CHE_STAT_RESUME      0x0003      /*RO*/
#define  CHE_STAT_BUSY        0x0004      /*RO*/

/*CHE_CDES*/
#define  CHE_CDES_MASK        0xffffffff

/*CHE_INTSTA*/
#define  CHE_INTSTA_OK        0x1
#define  CHE_INTSTA_FAIL      0x2
#define  CHE_INTSTA_RESUME    0x3   //??

/*CHE_INTEN*/
#define  CHE_INTEN_OK         0x1
#define  CHE_INTEN_FAIL       0x2

#define CHE_REGSET_START(_data)  \
{\
   DRV_WriteReg32(CHE_START, (_data));\
   che_hw_setting[CHE_HW_SETTING_START] = (_data);\
}

#define CHE_REGSET_INTEN(_data)  \
{\
   DRV_WriteReg32(CHE_INTEN, (_data));\
   che_hw_setting[CHE_HW_SETTING_INTEN] = (_data);\
}

#define CHE_REGSET_CON(_data)  \
{\
   DRV_WriteReg32(CHE_CON, (_data));\
   che_hw_setting[CHE_HW_SETTING_CON] = (_data);\
}

#define CHE_REGSET_KEY0(_data)  \
{\
   DRV_WriteReg32(CHE_IN0, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY0] = (_data);\
}

#define CHE_REGSET_KEY1(_data)  \
{\
   DRV_WriteReg32(CHE_IN1, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY1] = (_data);\
}

#define CHE_REGSET_KEY2(_data)  \
{\
   DRV_WriteReg32(CHE_IN2, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY2] = (_data);\
}

#define CHE_REGSET_KEY3(_data)  \
{\
   DRV_WriteReg32(CHE_IN3, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY3] = (_data);\
}

#define CHE_REGSET_KEY4(_data)  \
{\
   DRV_WriteReg32(CHE_IN0, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY4] = (_data);\
}

#define CHE_REGSET_KEY5(_data)  \
{\
   DRV_WriteReg32(CHE_IN1, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY5] = (_data);\
}

#define CHE_REGSET_KEY6(_data)  \
{\
   DRV_WriteReg32(CHE_IN2, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY6] = (_data);\
}

#define CHE_REGSET_KEY7(_data)  \
{\
   DRV_WriteReg32(CHE_IN3, (_data));\
   che_hw_setting[CHE_HW_SETTING_KEY7] = (_data);\
}

#define CHE_REGSET_CKEY(_data)  \
{\
   DRV_WriteReg32(CHE_IN3, (_data));\
   che_hw_setting[CHE_HW_SETTING_CKEY] = (_data);\
}

#define CHE_REGSET_IV0(_data)  \
{\
   DRV_WriteReg32(CHE_IN0, (_data));\
   che_hw_setting[CHE_HW_SETTING_IV0] = (_data);\
}

#define CHE_REGSET_IV1(_data)  \
{\
   DRV_WriteReg32(CHE_IN1, (_data));\
   che_hw_setting[CHE_HW_SETTING_IV1] = (_data);\
}

#define CHE_REGSET_IV2(_data)  \
{\
   DRV_WriteReg32(CHE_IN2, (_data));\
   che_hw_setting[CHE_HW_SETTING_IV2] = (_data);\
}

#define CHE_REGSET_IV3(_data)  \
{\
   DRV_WriteReg32(CHE_IN3, (_data));\
   che_hw_setting[CHE_HW_SETTING_IV3] = (_data);\
}

#define CHE_REGSET_SRC(_data)  \
{\
   DRV_WriteReg32(CHE_IN0, _data);\
   che_hw_setting[CHE_HW_SETTING_SRC] = (_data);\
}

#define CHE_REGSET_DST(_data)  \
{\
   DRV_WriteReg32(CHE_IN1, _data);\
   che_hw_setting[CHE_HW_SETTING_DST] = (_data);\
}

#define CHE_REGSET_LEN(_data)  \
{\
   DRV_WriteReg32(CHE_IN2, _data);\
   che_hw_setting[CHE_HW_SETTING_LEN] = (_data);\
}

#define CHE_REGSET_SADDR(_data)  \
{\
   DRV_WriteReg32(CHE_IN3, _data);\
   che_hw_setting[CHE_HW_SETTING_SADDR] = (_data);\
}

#define CHE_WAIT_STAT_OK()  \
{\
   kal_uint32 status;\
   while(DRV_Reg32(CHE_STAT) != CHE_STAT_OK);\
   status = DRV_Reg32(CHE_INTSTA);\
}

#define CHE_WAIT_STAT_RESUME()  \
{\
   kal_uint32 status;\
   while(DRV_Reg32(CHE_STAT) != CHE_STAT_RESUME);\
   status = DRV_Reg32(CHE_INTSTA);\
}

#endif