📄 ppp_framer.h
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PFC_ENCODE_PAUSE,
PFC_ENCODE_ERR
}pfc_encode_state_enum;
typedef struct{
kal_uint32 src;
kal_uint32 src_len; // number of undecode string.
kal_uint32 dst;
kal_uint32 dst_len; // number of unused destination buffer
kal_uint32 daccm;
kal_uint32 daccm_pre; // previous daccm
kal_uint32 esc_count;
kal_uint8 control;
kal_uint16 protocol; // store the protocol filed form frames
kal_bool df7e; // find until fisrt 0x7E appers
kal_bool dset7e; // allow ppp frame is not start with 0x7e for subsequent frames
kal_bool reset; // reset the decoder
kal_uint8 daccm_index[32]; // index 0~31 is escaped
}pfc_decode_cfg_struct;
typedef struct{
kal_uint32 src;
kal_uint32 src_len;
kal_uint32 dst;
kal_uint32 dst_len;
kal_uint32 eaccm; //stuffing control
kal_uint16 protocol; // encode with this protocol field
kal_uint16 is_last; // indicate last src or dest for encoding
kal_uint8 control;
kal_bool is_update;
}pfc_encode_cfg_struct;
typedef struct{
kal_uint8 id;
pfc_type_enum type; // use
}pfc_handler_struct;
typedef struct{
volatile pfc_state_enum state;
volatile pfc_status_enum status;
pfc_decode_state_enum decode_state;
pfc_encode_state_enum encode_state;
pfc_decode_cfg_struct decode_cfg;
pfc_encode_cfg_struct encode_cfg;
kal_uint8 slow_rate;
kal_uint8 gpt_handle;
volatile kal_bool is_timeout;
kal_uint32 handler;
// kal_hisrid hisr;
// kal_eventgrpid event;
}pfc_dcb_struct;
typedef struct{
kal_uint32 cur_src;
kal_uint32 cur_dst;
kal_uint32 un_read_len;
kal_uint32 un_write_len;
}pfc_report_struct;
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#endif // MT6228
#if defined(MT6229) || defined(MT6230)
#define PFC_START (PFC_BASE_ADRS+0x00) // start control register
#define PFC_CON (PFC_BASE_ADRS+0x04) // configuration register (ACFC, PFC..)
#define PFC_PTC (PFC_BASE_ADRS+0x08) // protocol field
#define PFC_ACCM (PFC_BASE_ADRS+0x0c) // ACCM bit register
#define PFC_SADDR (PFC_BASE_ADRS+0x10) // state address( for multi-context)
#define PFC_SRC (PFC_BASE_ADRS+0x14) // source address
#define PFC_USLEN (PFC_BASE_ADRS+0x18) // unused source length
#define PFC_DES (PFC_BASE_ADRS+0x1c) // destination address
#define PFC_UDLEN (PFC_BASE_ADRS+0x20) // unused destination length
#define PFC_INTEN (PFC_BASE_ADRS+0x24) // interrupt enable
#define PFC_STAT (PFC_BASE_ADRS+0x28) // interrupt status
#define PFC_SDRAT (PFC_BASE_ADRS+0x2c) // slow down rate
#define PFC_START_ENABLE (0x0001) // PFC start
#define PFC_START_CLR (0x0002) // reset all status
#define PFC_START_DSET7E (0x0004) // set 0x7E is found mode(decode a frame with 0x7E is dorpped)
#define PFC_START_DF7E (0x0008) // find first occurence of 0x7e
#define PFC_START_ELASTS (0x0010) // end the process after the source data ran out
#define PFC_START_ELASTD (0x0020) // end the process after the destination data ran out
#define PFC_START_WSTAT (0x0040) // write the PFC internal status into SADDR at the end of the process
#define PFC_START_RSTAT (0x0080) // Read the PFC internal status from SADRR at the begining of the process
#define PFC_START_M_SRC (0x0100) // mask of the source address while restoring the status
#define PFC_START_M_SL (0x0200) // mask of the USLEN
#define PFC_START_M_DES (0x0400) // mask of the destination address
#define PFC_START_M_DL (0x0800) // mask of the UDLEN
#define PFC_START_M_ALL (0x0f00) // mask all
#define PFC_CON_ENC (0x0001) // encode bit
#define PFC_CON_ACFC (0x0002) // ACFC is enabled
#define PFC_CON_PFC (0x0004) // PFC is enabled
#define PFC_CON_F32 (0x0008) // using FCS32 otherwise FCS16
#define PFC_CON_EDEL (0x0010) // Escape DEL(0x7f) in encoding
// for adaptation to MT6228
#define PFC_CON_DACFC (PFC_CON_ACFC)
#define PFC_CON_DPFC (PFC_CON_PFC)
#define PFC_CON_DF32 (PFC_CON_F32)
#define PFC_CON_EACFC (PFC_CON_ACFC)
#define PFC_CON_EPFC (PFC_CON_PFC)
#define PFC_CON_EF32 (PFC_CON_F32)
#define PFC_PTC_8bit (0x00ff) // if PFC is enabled
#define PFC_INTEN_OK (0x01) // interrupt occurs when PFC finished in OK or RESUME
#define PFC_INTEN_ERR (0x02) // interrupt occures when any error occurs.
#define PFC_INTEN_ALL (0x3)
#define PFC_EVENT 1
#define PFC_START_RESET_VALUE 0
#define PFC_DECODE_START_VALUE (PFC_START_DUPSRL|PFC_START_ENABLE)
#define PFC_ENCODE_START_VALUE (PFC_START_EUPSRL|PFC_START_ENABLE)
//#define PFC_WAIT_COMPLETE() while(*(volatile kal_uint32*)PFC_STAT == PFC_STAT_BUSY);
#define PFC_WAIT_COMPLETE() while((pfc_dcb.status = DRV_Reg(PFC_STAT))==PFC_STAT_BUSY \
&& !pfc_dcb.is_timeout);
#define PFC_DECODE_RESET() DRV_WriteReg(PFC_START, PFC_START_CLR);\
DRV_WriteReg(PFC_START, 0);
#define PFC_ENCODE_RESET() DRV_WriteReg(PFC_START, PFC_START_CLR);\
DRV_WriteReg(PFC_START, 0);
#define HI_BYTE(a) (kal_uint8)(((a)>>8)&0xff)
#define LOW_BYTE(a) (kal_uint8)(((a))&0xff)
#define PPP_ERR_SYNC -102 // incorrect sequence flag
#define PPP_ERR_FCS -100 // incorrect FCS
#define PPP_ERR_ACF_PROTOCOL -101 // incorrect address control field
#define PFC_RESET() DRV_WriteReg(PFC_START, PFC_START_CLR);
//DRV_WriteReg(PFC_START, 0);
// #define PPP_PUSH(x) async_Encode(p->eaccm,&co,(x), del)
typedef enum{
PFC_STAT_OK = 0, // PFC is ready
PFC_STAT_BUSY = 1, // PFC is busy
PFC_STAT_DST_FULL = 2, // destination buffer is full
PFC_STAT_DSRC_ZERO_LEN = 3, // decode zero length of src operation
PFC_STAT_FCS_ERR = 4, // decode with a error FCS
PFC_STAT_NOT_0x7E = 5, // decode a not 0x7e leading sequence
PFC_STAT_AC_ERR = 6, // address or control filed failed
PFC_STAT_INVALID_FRAME = 7, // invalid 0x7d, 0x7e sequence
PFC_STAT_PAUSE = 8, // PFC is at pause state
// software added
PFC_TIMEOUT_STA = 100
}pfc_status_enum;
#define PFC_STATUE_DECODE_RESUME_FAIL -1
#define PFC_CONTEXT_SIZE 28
typedef enum{
PFC_READY_STATE,
PFC_DECODE_STATE,
PFC_ENCODE_STATE,
PFC_ERROR_STATE
}pfc_state_enum;
typedef enum{
PFC_DECODE_READY,
PFC_DECODE_BUSY,
PFC_DECODE_PAUSE,
PFC_DECODE_ERR,
PFC_DECODE_FIND_NO_7E
}pfc_decode_state_enum;
typedef enum{
// PFC_ENCODE_IDLE,
PFC_ENCODE_READY,
PFC_ENCODE_BUSY,
PFC_ENCODE_PAUSE,
PFC_ENCODE_COMPLETE,
PFC_ENCODE_ERR
}pfc_encode_state_enum;
typedef struct{
kal_uint32 src;
kal_uint32 src_len;
kal_uint32 dst;
kal_uint32 dst_len;
kal_uint32 daccm; // escape the enabled bits.
kal_uint16 protocol; // store the protocol filed form frames
kal_uint16 start;
kal_uint8 control;
kal_bool df7e; // find until fisrt 0x7E appers
kal_bool dset7e; // allow ppp frame is not start with 0x7e for subsequent frames
kal_bool reset; // reset the decoder
}pfc_decode_cfg_struct;
typedef struct{
kal_uint32 src;
kal_uint32 src_len;
kal_uint32 dst;
kal_uint32 dst_len;
kal_uint32 eaccm; //stuffing control
kal_uint16 protocol; // encode with this protocol field
kal_uint16 is_last; // indicate last src or dest for encoding
kal_uint16 start;
kal_uint8 control;
}pfc_encode_cfg_struct;
typedef struct{
kal_uint32 cur_src;
kal_uint32 cur_dst;
kal_uint32 read_len;
kal_uint32 write_len;
}pfc_report_struct;
typedef struct{
kal_uint32 d_buf[PFC_CONTEXT_SIZE/sizeof(kal_uint32)]; // decode context buffer
// kal_uint32 e_buf[PFC_CONTEXT_SIZE/sizeof(kal_uint32)]; // encode context buffer
pfc_status_enum status;
pfc_decode_state_enum d_state;
pfc_encode_state_enum e_state;
pfc_encode_cfg_struct encode_cfg;
pfc_decode_cfg_struct decode_cfg;
}pfc_id_struct;
typedef struct{
volatile pfc_state_enum state;
volatile pfc_status_enum status;
kal_uint8 gpt_handle;
volatile kal_bool is_timeout;
pfc_id_struct id[PFC_MAX_ID];
}pfc_dcb_struct;
#endif // MT6229
extern kal_uint8 ppp_frame_open(pfc_owner_id_enum owner);
extern void ppp_frame_close(kal_uint32 id);
extern kal_bool ppp_frame_encode_all(ppp_buff_head_struct *dst,
ppp_buff_head_struct* src, ahdlc_state_struct* state, kal_uint8 id);
extern kal_bool ppp_frame_decode_all(ppp_buff_head_struct *dst,
ppp_buff_head_struct *src, ahdlc_state_struct *state, kal_bool * is_ath,kal_uint8 id);
#endif
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