usb_hw.h

8032底层驱动部分。因为可以移植 所以单独来拿出来

#define VUSB_INT_ENB_STALL			(0x80)

/* VUSB Fast mode error status register masks */
#define USB_FM_ERR_STA_OVR_FLW		(0x80)
#define VUSB_FM_ERR_STAT_TOKEN_DONE	(0x40)
#define VUSB_FM_ERR_SUC_ERR			(0x04)
#define VUSB_FM_ERR_NAK_ERR			(0x02)
#define VUSB_FM_ERR_SHORT_ERR		(0x01)

/* VUSB Fast mode control register masks */
#define VUSB_FM_CTL_FMENB			(0x1)
#define VUSB_FM_CTL_SUCERREN		(0x8)
#define VUSB_FM_CTL_EP_RX_ODD_SHIFT		1
#define VUSB_FM_CTL_EP_TX_ODD_SHIFT		2
#define VUSB_FM_CTL_EP_TOG_BIT_SHIFT	6

/* VUSB Fast mode endpoint register masks*/
#define VUSB_FM_EP_TX				(0x10)
#define VUSB_FM_EP_TX_RES			(0x80)
#define VUSB_FM_EP_ENDPT_MASK		(0x0f)

/* VUSB FM DMA index */
#define VUSB_FM_DMA_RX1				0
#define VUSB_FM_DMA_TX1				1
#define VUSB_FM_DMA_RX2				2
#define VUSB_FM_DMA_TX2				3

/* VUSB EXTRA register masks*/
#define VUSB_PHY_RESUME_INT			(0x80)	
#define VUSB_PHY_RESUME_INT_ENB		(0x04)
#define VUSB_PHY_SUSPEND			(0x02)

/* VUSB SOFT RST register masks*/
#define VUSB_SOFT_RST_EN			(0x01)

/* VUSB BDT masks */
#define VUSB_BDT_OWNS_BIT			(1 << 7)
#define VUSB_BDT_DATA01_BIT			(1 << 6)
#define VUSB_BDT_KEEP_BIT			(1 << 5)
#define VUSB_BDT_NINC_BIT			(1 << 4)
#define VUSB_BDT_DTS_BIT			(1 << 3)
#define VUSB_BDT_STALL_BIT			(1 << 2)
#define VUSB_BDT_BC_SHIFT			16
#define VUSB_BDT_DATA01_SHIFT		6
#define VUSB_BDT_BC_MASK			0x03ff0000
             
#define VUSB_BDT_PID_MASKS			(0x3C)
#define VUSB_BDT_NAK_PID			(0x28)
#define VUSB_BDT_ERROR_PID			(0x3c)
#define VUSB_BDT_STALL_PID			(0x38)
#define VUSB_BDT_BUS_TIMEOUT_PID	(0x00)


/* OTG Interrupt Status Register Bit Masks */
#define  OTG_INT_STATUS_A_VBUS				(0x01)
#define  OTG_INT_STATUS_B_SESS_END			(0x04)
#define  OTG_INT_STATUS_SESS_VLD			(0x08)
#define  OTG_INT_STATUS_LINE_STATE_CHANGE	(0x20)
#define  OTG_INT_STATUS_1_MSEC				(0x40)
#define  OTG_INT_STATUS_ID					(0x80)

/* OTG Interrupt Enable Register Bit Masks */
#define  OTG_INT_ENABLE_A_VBUS				(0x01)
#define  OTG_INT_ENABLE_B_SESS_END			(0x04)
#define  OTG_INT_ENABLE_SESS_VLD			(0x08)
#define  OTG_INT_ENABLE_1_MSEC				(0x40)
#define  OTG_INT_ENABLE_ID					(0x80)

/*OTG Status register masks*/
#define  OTG_STATUS_A_VBUS					(0x01)
#define  OTG_STATUS_B_SESS_END				(0x04)
#define  OTG_STATUS_SESS_VLD				(0x08)
#define  OTG_STATUS_LINE_STATE_CHANGE		(0x20)
#define  OTG_STATUS_1_MSEC					(0x40)
#define  OTG_STATUS_ID						(0x80)

/*OTG Control register masks*/
#define  OTG_CTL_VBUS_DSCHG					(0x01)
#define  OTG_CTL_VBUS_CHG					(0x02)
#define  OTG_CTL_OTG_ENABLE					(0x04)
#define  OTG_CTL_VBUS_ON					(0x08)
#define  OTG_CTL_DM_LOW						(0x10)
#define  OTG_CTL_DP_LOW						(0x20)
#define  OTG_CTL_DM_HIGH					(0x40)
#define  OTG_CTL_DP_HIGH					(0x80)


/* Token register masks */
#define  VUSB_TOKEN_ENDPT					(0x0f)
#define  VUSB_TOKEN_PID						(0xf0)
#define  VUSB_TOKEN_OUT						(0x10)
#define  VUSB_TOKEN_IN						(0x90)
#define  VUSB_TOKEN_SETUP					(0xd0)

#else /* MT6228 || MT6229 || MT6230*/

#define USB_FADDR		(USB_base+0x0)
#define USB_POWER		(USB_base+0x1)
#define USB_INTRIN1		(USB_base+0x2)	/*status, read only*/
#define USB_INTRIN2		(USB_base+0x3) 	/*status, read only*/
#define USB_INTROUT1	(USB_base+0x4) 	/*status, read only*/
#define USB_INTROUT2	(USB_base+0x5) 	/*status, read only*/
#define USB_INTRUSB		(USB_base+0x6) 	/*status, read only*/
#define USB_INTRIN1E	(USB_base+0x7)
#define USB_INTRIN2E	(USB_base+0x8)
#define USB_INTROUT1E	(USB_base+0x9)
#define USB_INTROUT2E	(USB_base+0xa)
#define USB_INTRUSBE	(USB_base+0xb)
#define USB_FRAME1		(USB_base+0xc)	/*read only*/
#define USB_FRAME2		(USB_base+0xd)	/*read only*/ /*Max Frame length = 11 bits*/
#define USB_INDEX		(USB_base+0xe)	/*RW, 4bit available*/
#define USB_RSTCTRL		(USB_base+0xf)

#define USB_INMAXP		(USB_base+0x10)	/*RW*/
#define USB_CSR0		(USB_base+0x11)
#define USB_INCSR1		(USB_base+0x11)
#define USB_INCSR2		(USB_base+0x12)
#define USB_OUTMAXP		(USB_base+0x13)	/*RW*/
#define USB_OUTCSR1		(USB_base+0x14)
#define USB_OUTCSR2		(USB_base+0x15)
#define USB_COUNT0		(USB_base+0x16)	/*RO, EP0 only*/
#define USB_OUTCOUNT1	(USB_base+0x16)   
#define USB_OUTCOUNT2	(USB_base+0x17)	/*RO,11bits*/

#define USB_EP0			(USB_base+0x20)	/*4 byte as 1 queue*/
#define USB_EP1			(USB_base+0x24)
#define USB_EP2			(USB_base+0x28)
#define USB_EP3			(USB_base+0x32)
#define USB_ENABLE		(USB_base+0x230)

/*USB_FADDR*/
#define USB_FADDR_ADDRMASK		(0x7f)   /*RO*/
#define USB_FADDR_UPDATE		(0x80)   /*RW*/

/*USB_POWER*/
#define USB_POWER_SETSUSPEND	(0x01)   /*RW*/
#define USB_POWER_SUSPENDSTAT	(0x02)   /*RO*/ /*Read clear by the intr. register*/
#define USB_POWER_RESUME		(0x04)   /*RW*/
#define USB_POWER_RESET			(0x08)   /*RO*/
#define USB_POWER_SWRSTENAB		(0x10)   /*RW*/
#define USB_POWER_ISOUPDATE		(0x80)   /*RW*/

/*USB_RSTCTRL*/
#define USB_RSTCTRL_SWRST		(0x80)	 /*RW*/ 

/*USB_INTRIN1, USB_INTRIN2 is not needed*/   
#define USB_INTRIN1_EP0			(0x01)   /*RO*/
#define USB_INTRIN1_EP1			(0x02)   /*RO*/
#define USB_INTRIN1_EP2			(0x04)   /*RO*/
#define USB_INTRIN1_EP3			(0x08)   /*RO*/

/*USB_INTROUT1, USB_INTROUT2 is not needed*/
#define USB_INTROUT1_EP1		(0x02)   /*RO*/
#define USB_INTROUT1_EP2		(0x04)   /*RO*/

/*USB_INTRUSB*/
#define USB_INTRUSB_SUSPEND		(0x01)   /*RO*/
#define USB_INTRUSB_RESUME		(0x02)   /*RO*/
#define USB_INTRUSB_RESET		(0x04)   /*RO*/
#define USB_INTRUSB_SOF			(0x08)   /*RO*/

/*USB_INTRIN1E, USB_INTRIN2E is not needed*/
#define USB_INTRIN1E_EP0		(0x01)   /*RW*/
#define USB_INTRIN1E_EP1		(0x02)   /*RW*/
#define USB_INTRIN1E_EP2		(0x04)   /*RW*/

/*USB_INTROUT1E, USB_INTROUT2E is not needed*/
#define USB_INTROUT1E_EP0		(0x01)   /*RW*/
#define USB_INTROUT1E_EP1		(0x02)   /*RW*/
#define USB_INTROUT1E_EP2		(0x04)   /*RW*/

/*USB_INTRUSBE*/
#define USB_INTRUSBE_SUSPEND	(0x01)   /*RW*/
#define USB_INTRUSBE_RESUME		(0x02)   /*RW*/
#define USB_INTRUSBE_RESET		(0x04)   /*RW*/
#define USB_INTRUSBE_SOF		(0x08)   /*RW*/

/*USB_INMAXP*/
#define USB_INMAXP_MASK			(0xff)   /*RW*/

/*USB_OUTMAXP*/
#define USB_OUTMAXP_MASK		(0xff)   /*RW*/

/*USB_CSR0*/
#define USB_CSR0_OUTPKTRDY				(0x01)   /*RO*/
#define USB_CSR0_INPKTRDY				(0x02)   /*RW,AC*/
#define USB_CSR0_SENTSTALL				(0x04)   /*RC*/
#define USB_CSR0_DATAEND				(0x08)   /*WO,AC*/
#define USB_CSR0_SETUPEND				(0x10)   /*RO*/
#define USB_CSR0_SENDSTALL				(0x20)   /*WO,AC*/
#define USB_CSR0_SERVICEDOUTPKTRDY		(0x40)   /*WO,AC*/
#define USB_CSR0_SERVICESETUPEND		(0x80)   /*WO,AC*/

/*USB_INCSR1*/
#define USB_INCSR1_INPKTRDY				(0x01)   /*RW*/
#define USB_INCSR1_FIFONOTEMPTY			(0x02)   /*RC*/
#define USB_INCSR1_UNDERRUN				(0x04)   /*RC*/
#define USB_INCSR1_FLUSHFIFO			(0x08)   /*WO*/
#define USB_INCSR1_SENDSTALL			(0x10)   /*RW*/
#define USB_INCSR1_SENTSTALL			(0x20)   /*RC*/
#define USB_INCSR1_CLRDATATOG			(0x40)   /*WO*/

/*USB_INCSR2*/
#define USB_INCSR2_FRCDATATOG			(0x08)   /*RW*/
#define USB_INCSR2_DMAENAB				(0x10)   /*RW*/
#define USB_INCSR2_MODE					(0x20)   /*RW*/
#define USB_INCSR2_ISO					(0x40)   /*RW*/
#define USB_INCSR2_AUTOSET				(0x80)   /*RW*/

/*USB_OUTCSR1*/
#define USB_OUTCSR1_OUTPKTRDY			(0x01)   /*RC*/
#define USB_OUTCSR1_FIFOFULL			(0x02)   /*R,AC*/
#define USB_OUTCSR1_OVERRUN				(0x04)   /*RC*/
#define USB_OUTCSR1_DATAERROR			(0x08)   /*RO*/
#define USB_OUTCSR1_FLUSHFIFO			(0x10)   /*WO,AC*/
#define USB_OUTCSR1_SENDSTALL			(0x20)   /*RW*/
#define USB_OUTCSR1_SENTSTALL			(0x40)   /*RC*/
#define USB_OUTCSR1_CLRDATATOG			(0x80)   /*WO*/

/*USB_OUTCSR2*/
#define USB_OUTCSR2_DMAMODE				(0x10)   /*RW*/
#define USB_OUTCSR2_DMAENAB				(0x20)   /*RW*/
#define USB_OUTCSR2_ISO					(0x40)   /*RW*/
#define USB_OUTCSR2_AUTOCLEAR			(0x80)   /*RW*/

/*USB_ENABLE*/
#define USB_ENABLE_EN					(0x1)   /*WO*/
#define USB_ENABLE_DIS					(0x0)   /*WO*/

#endif /* MT6228 || MT6229 || MT6230*/

#endif  /* USB_HW_H */