nand_mtd.h

8032底层驱动部分。因为可以移植 所以单独来拿出来

/*****************************************************************************
*  Copyright Statement:
*  --------------------
*  This software is protected by Copyright and the information contained
*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2005
*
*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
*
*****************************************************************************/

/*******************************************************************************
 *
 * Filename:
 * ---------
 *	NandMTD.h
 *
 * Project:
 * --------
 *   MAUI
 *
 * Description:
 * ------------
 *   This is a NAND Flash MTD driver header file for Samsung and Toshiba flash devices.
 *
 * Author:
 * -------
 * -------
 * -------
 *
 *==============================================================================
 * 				HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *------------------------------------------------------------------------------
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 *
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 *------------------------------------------------------------------------------
 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *==============================================================================
 *******************************************************************************/

#ifndef NAND_MTD_H
#define NAND_MTD_H


/*******************************************************************************
 * Include Header Files
 *******************************************************************************/
#include "reg_base.h"
#include "drvpdn.h"

/*******************************************************************************
 * define
 *******************************************************************************/

#ifndef NODEBUG
   #define DEBUG
#endif

#ifdef _MSC_VER
   #define INTERN _fastcall
   #define WATCOM_VOLATILE
#elif defined __BORLANDC__
   #define INTERN __fastcall
   #define WATCOM_VOLATILE
#else
   #define INTERN
   #define WATCOM_VOLATILE volatile   // Watcom compiler bug workaround
#endif


#define MTD_STATUS_ERROR           (0)
#define MTD_STATUS_NO_ERROR        (1)
#define MTD_STATUS_CORRECTED       (2)
#define MTD_STATUS_ID_NOT_SUPPORT     (10)

/* NAND flash copy back support */
#define PAGE_COPY_SUPPORT 1
#define MAX_PAGE_BUFFER_SIZE  (2048)
#define MAX_SPARE_BUFFER_SIZE (64)
/* NAND flash plane setting */
#define NAND_PLANE_BLOCK_BIT0 (1 << 0)
#define NAND_PLANE_BLOCK_BIT1 (1 << 1)
#define NAND_PLANE_BLOCK_BIT2 (1 << 2)
#define NAND_PLANE_BLOCK_BIT3 (1 << 3)
#define NAND_PLANE_BLOCK_BIT4 (1 << 4)
#define NAND_PLANE_BLOCK_BIT5 (1 << 5)
#define NAND_PLANE_BLOCK_BIT6 (1 << 6)
#define NAND_PLANE_BLOCK_BIT7 (1 << 7)
#define NAND_PLANE_BLOCK_BIT8 (1 << 8)
#define NAND_PLANE_BLOCK_BIT9 (1 << 9)
#define NAND_PLANE_BLOCK_BIT10 (1 << 10)
#define NAND_PLANE_BLOCK_BIT11 (1 << 11)
#define NAND_PLANE_BLOCK_BIT12 (1 << 12)
#define NAND_PLANE_BLOCK_BIT13 (1 << 13)
#define NAND_PLANE_BLOCK_BIT14 (1 << 14)
#define NAND_PLANE_BLOCK_BIT15 (1 << 15)
#define NAND_PLANE_BLOCK_BIT16 (1 << 16)
/*******************************************************************************
 * NFI address definition
 *******************************************************************************/
#define DMA_NFI  0xf

#if ((defined(MT6228)) || (defined(MT6229)) )
#define NFI_GPIO_CON    ((volatile UINT16P)(0x801201D0))		// gpio control pin
#define NFI_GPIO_DATA1  ((volatile UINT16P)(0x80120200))		// data bit 8-9
#define NFI_GPIO_DATA2  ((volatile UINT16P)(0x80120210))		// data bit 10-15
#elif ((defined(MT6219))|| (defined(MT6226))|| (defined(MT6226M)) || (defined(MT6227)))
#define NFI_GPIO_CON    ((volatile UINT16P)(0x80120180))
#else   //MT6217, MT6218B 
#define NFI_GPIO_CON    ((volatile UINT16P)(0x80120130))
#endif

#define NFI_base        (0x80090000)
#define NFI_ACCCON      ((volatile UINT16P)(NFI_base+0x0000))
#define NFI_PAGEFMT     ((volatile UINT16P)(NFI_base+0x0004))
#define NFI_OPCON       ((volatile UINT16P)(NFI_base+0x0008))
#define NFI_CMD         ((volatile UINT16P)(NFI_base+0x000C))
#define NFI_ADDNOB      ((volatile UINT16P)(NFI_base+0x0010))
#define NFI_ADDRL       ((volatile UINT32P)(NFI_base+0x0014))
#define NFI_ADDRM       ((volatile UINT16P)(NFI_base+0x0018))
#define NFI_DATAW       ((volatile UINT32P)(NFI_base+0x001C))
#define NFI_DATAWB      ((volatile UINT16P)(NFI_base+0x0020))
#define NFI_DATAR       ((volatile UINT32P)(NFI_base+0x0024))
#define NFI_DATARB		((volatile UINT16P)(NFI_base+0x0028))
#define NFI_PSTA        ((volatile UINT16P)(NFI_base+0x002C))
#define NFI_FIFOCON     ((volatile UINT16P)(NFI_base+0x0030))
#define NFI_CON         ((volatile UINT16P)(NFI_base+0x0034))
#define NFI_INTR        ((volatile UINT16P)(NFI_base+0x0038))
#define NFI_INTR_EN     ((volatile UINT16P)(NFI_base+0x003C))
#define NFI_PAGECNTR		((volatile UINT16P)(NFI_base+0x0040))
#define NFI_ADDRCNTR		((volatile UINT16P)(NFI_base+0x0044))
#define NFI_SYM0_ADDR   ((volatile UINT16P)(NFI_base+0x0050))
#define NFI_SYM1_ADDR   ((volatile UINT16P)(NFI_base+0x0054))
#define NFI_SYM2_ADDR   ((volatile UINT16P)(NFI_base+0x0058))
#define NFI_SYM3_ADDR   ((volatile UINT16P)(NFI_base+0x005C))
#define NFI_SYM0_DAT    ((volatile UINT32P)(NFI_base+0x0060))
#define NFI_SYM1_DAT    ((volatile UINT32P)(NFI_base+0x0064))
#define NFI_SYM2_DAT    ((volatile UINT32P)(NFI_base+0x0068))
#define NFI_SYM3_DAT    ((volatile UINT32P)(NFI_base+0x006C))
#define NFI_ERRDET      ((volatile UINT16P)(NFI_base+0x0070))
#define NFI_PAR0        ((volatile UINT16P)(NFI_base+0x0080))
#define NFI_PAR1        ((volatile UINT16P)(NFI_base+0x0084))
#define NFI_PAR2        ((volatile UINT16P)(NFI_base+0x0088))
#define NFI_PAR3        ((volatile UINT16P)(NFI_base+0x008C))
#define NFI_PAR4        ((volatile UINT16P)(NFI_base+0x0090))
#define NFI_PAR5        ((volatile UINT16P)(NFI_base+0x0094))
#define NFI_PAR6        ((volatile UINT16P)(NFI_base+0x0098))
#define NFI_PAR7        ((volatile UINT16P)(NFI_base+0x009C))
#define NFI_CSEL			((volatile UINT16P)(NFI_base+0x0100))

/*******************************************************************************
 * NFI register definition
 *******************************************************************************/
/* NFI_ACCCON - example
	*NFI_ACCCON = ACCCON | (((NFI_W2R<<6)|(NFI_WH<<4)) | ((NFI_WST<<2)|NFI_RLC));

	*NFI_ACCCON = 0x07C6	// C2R=111, W2R=11, WH=00, WST=00, RLT=10

*/
#define ACCCON						0x0700	// C2R=111
#define NFI_W2R					3			// 0:2T, 1:4T, 2:6T, 3:8T ; recommanded value=3
#define NFI_WH						3			// 0:0T, 1:1T, 2:2T, 3:3T ; recommanded value=1
#define NFI_WST					3			// 0:0T, 1:1T, 2:2T, 3:3T ; recommanded value=1
#define NFI_RLC					3			// 0:0T, 1:1T, 2:2T, 3:3T ; recommanded value=2

/* NFI_PAGEFMT; support for PAGEFMT_PageSize_BusWidth */
#define PAGEFMT_512_8BIT   	0x0020
#define PAGEFMT_512_16BIT  	0x0120
#define PAGEFMT_2K_8BIT			0x0025
#define PAGEFMT_2K_16BIT		0x0125

#define	IO_ACCESS_8BIT			8
#define	IO_ACCESS_16BIT		16

/* NFI_OPCON */
#define BURST_RD           	0x0001
#define BURST_WR           	0x0002
#define ECC_RD_INIT        	0x0010
#define ECC_WR_INIT        	0x0020
#define SINGLE_RD          	0x0100
#define NOB_BYTE           	0x1000
#define NOB_WORD           	0x2000
#define NOB_DWORD          	0x0000

/* Nand flash command */
#define RD_1ST_CMD         	0x00
#define RD_2ND_HALF_CMD     	0x01	// only for 512B page-size
#define RD_SPARE_CMD       	0x50	// only for 512B page-size
#define RD_2ND_CYCLE_CMD		0x30	// only for 2KB  page-size
#define INPUT_DATA_CMD     	0x80
#define PROG_DATA_CMD      	0x10
#define BLOCK_ERASE1_CMD   	0x60
#define BLOCK_ERASE2_CMD   	0xD0
#define RD_ID_CMD          	0x90
#define RD_STATUS_CMD      	0x70
#define RESET_CMD          	0xFF
#define CP_READ_CMD        	0x35
#define CP_INPUT_CMD_2K    	0x85
#define CP_INPUT_CMD_512   	0x8A
#define CP_PROG_CMD_TOSHIBA	0x15

/* NFI_PSTA */
#define STATUS_CMD         	0x1
#define STATUS_ADDR        	0x2
#define STATUS_DATAR       	0x4
#define STATUS_DATAW       	0x8
#define STATUS_BUSY        	0x100

/* NFI_FIFOCON */
#define RD_EMPTY_MASK      	0x001
#define RD_FULL_MASK       	0x002
#define WR_EMPTY_MASK      	0x004
#define WR_FULL_MASK      		0x008
#define FIFO_FLUSH         	0x010
#define RESET              	0x020