📄 dmc_asm.s
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;/*************************************************************************************
;
; Project Name : S3C6410 Validation
;
; Copyright 2006 by Samsung Electronics, Inc.
; All rights reserved.
;
; Project Description :
; This software is only for validating functions of the S3C6410.
; Anybody can use this software without our permission.
;
;--------------------------------------------------------------------------------------
;
; File Name : dmc_asm.s
;
; File Description : This file implements the startup procedure.
;
; Author : Wonjoon jang
; Dept. : AP Development Team
; Created Date : 2007/01/31
; Version : 0.1
;
; History
; - Created(Wonjoon.jang 2007/01/31)
;
;*************************************************************************************/
GET Option.inc
GET sfr6410.inc
;////////////////////////////////////////////////////////////////////////////////
;// Definitions for DRAM Parameter
;// mSDR: K4S51163-F75 (32MB X 16)
;// mDDR: K4X51163PC (32MB X 16) X 2
;////////////////////////////////////////////////////////////////////////////////
; SDR Parameter
SDR_tREFRESH EQU 7800 ; ns
SDR_tRAS EQU 50 ; ns (min: 50ns)
SDR_tRC EQU 73 ; ns (min:72.5ns)
SDR_tRCD EQU 23 ; ns (min:22.5ns)
SDR_tRFC EQU 80 ; ns (min: 80ns)
SDR_tRP EQU 23 ; ns (min: 22.5ns)
SDR_tRRD EQU 15 ; ns (min: 15ns)
SDR_tXSR EQU 120 ; ns (min: 120ns)
SDR_CASL EQU 3 ; CAS Latency 3
; DDR Parameter
[ (1 = 1)
DDR_tREFRESH EQU 7800 ; ns 7800
DDR_tRAS EQU 45 ; ns (min: 45ns)
DDR_tRC EQU 68 ; ns (min: 67.5ns)
DDR_tRCD EQU 23 ; ns (min: 22.5ns)
DDR_tRFC EQU 80 ; ns (min: 80ns)
DDR_tRP EQU 23 ; ns (min: 22.5ns)
DDR_tRRD EQU 15 ; ns (min: 15ns)
DDR_tWR EQU 15 ; ns (min: 15ns)
DDR_tXSR EQU 120 ; ns (min: 120ns)
;DDR_tXSR EQU 200 ; ns (min: 120ns) ; test
]
[ (1 = 0)
DDR_tREFRESH EQU 7500 ; ns
DDR_tRAS EQU 60 ; ns (min: 45ns)
DDR_tRC EQU 80 ; ns (min: 67.5ns)
DDR_tRCD EQU 30 ; ns (min: 22.5ns)
DDR_tRFC EQU 90 ; ns (min: 80ns)
DDR_tRP EQU 30 ; ns (min: 22.5ns)
DDR_tRRD EQU 25 ; ns (min: 15ns)
DDR_tWR EQU 25 ; ns (min: 15ns)
DDR_tXSR EQU 120 ; ns (min: 120ns)
]
DDR_CASL EQU 3 ; CAS Latency 3
;////////////////////////////////////////////////////////////////////////////////
;// Definitions for memory configuration
;////////////////////////////////////////////////////////////////////////////////
;// Memory Configuration Register
;// CKE_Ctrl[31], Active_Chip[22:21], Qos_master[20:18], Burst[17:15], Stop_mem_clock[14]
;// Auto_power_down[13], Pwr_down_prd[12:7], AP bit[6], Row bit[5:3], Column bit[2:0]
;// CKE_Ctrl : 1'b0(One CKE Ctrl), 1'b1(Individual CKE Ctrl)
;// Active Chip : 2'b00 (1chip), 2'b01(2chips)
;// Memory Burst: 3'b000 (Burst1), 3'b001(Burst2), 3'b010(Burst4), 3'b011(Burst8), 3'b100(Burst16)
DMC1_MEM_CFG EQU ((0<<31)|(0<<22)|(0<<18)|(2<<15)|(0<<14)|(0<<13)|(0<<7)|(0<<6)|(2<<3)|(2<<0))
;DMC1_MEM_CFG EQU 0x80010012
;DMC1_MEM_CFG EQU ((0<<31)|(0<<22)|(0<<18)|(2<<15)|(0<<14)|(0<<13)|(0<<7)|(0<<6)|(2<<3)|(2<<0))
;// Memory Configuration 2 Register
;// Read Delay[12:11], Memory Type[10:8], Memory Width[7:6], Bank bits[5:4], DQM init[2], Clock[1:0]
;// Read Delay : 2'b00 (SDRAM), 2'b01 (DDR,mDDR), 2'b10 = Read Delay 2 cycle
;// Memory Type: 3'b000(SDRAM), 3'b001(DDR), 3'b011(mDDR), 3'b010(Embedded DRAM)
;// Memory Width : 2'b00 (16bit), 2'b01(32bit)
;// DQM init : DQM state at reset
;// Clock Config: AXI and Memory Clock are sync.
DMC1_MEM_CFG2 EQU ((1<<11)|(3<<8)|(1<<6)|(0<<4)|(1<<2)|(1<<0))
;DMC1_MEM_CFG2 EQU 0xB41
;// CHIP Configuration Register
;// BRC_RBC[16], Addr_match[15:8], Addr_Mask[7:0]
;// BRC_RBC: 1'b0 (Row-Bank-Column), 1'b1 (Bank-Row-Column)
;// Addr_match: AXI_addr[31:24], Ex) 0x5000_0000, Set 0x50
;// Addr_Mask : AXI_addr[31:24], Ex) 0x57ff_ffff, Set 0xF8
DMC1_CHIP0_CFG EQU ((1<<16)|(0x50<<8)|(0xF8<<0))
;// User Configuration Register
;// DQS3[7:6], DQS2[5:4], DQS1[3:2], DQS0[1:0]
DMC1_USER_CFG EQU 0x0;
;////////////////////////////////////////////////////////////////////////////////
;// Memory Chip direct command
;////////////////////////////////////////////////////////////////////////////////
DMC_NOP0 EQU 0x0c0000
DMC_NOP1 EQU 0x1c0000
DMC_PA0 EQU 0x000000 ;Precharge all
DMC_PA1 EQU 0x100000
DMC_AR0 EQU 0x040000 ;Autorefresh
DMC_AR1 EQU 0x140000
DMC_SDR_MR0 EQU 0x080032 ;MRS, CAS 3, Burst Length 4
;DMC_SDR_MR0 EQU 0x080033 ;MRS, CAS 3, Burst Length 8
DMC_SDR_MR1 EQU 0x180032
DMC_DDR_MR0 EQU 0x080162
DMC_DDR_MR1 EQU 0x180162
DMC_mDDR_MR0 EQU 0x080032 ;CAS 3, Burst Length 4
;DMC_mDDR_MR0 EQU 0x080033
DMC_mDDR_MR1 EQU 0x180032
DMC_mSDR_EMR0 EQU 0x0a0000 ;EMRS, DS:Full, PASR:Full Array
DMC_mSDR_EMR1 EQU 0x1a0000
DMC_DDR_EMR0 EQU 0x090000
DMC_DDR_EMR1 EQU 0x190000
DMC_mDDR_EMR0 EQU 0x0a0000 ; DS:Full, PASR:Full Array
DMC_mDDR_EMR1 EQU 0x1a0000
;////////////////////////////////////////////////////////////////////////////////
;// Memory Configurations for DMC
;// (HCLK: DMC Clock)
;////////////////////////////////////////////////////////////////////////////////
;// SDR , mSDR memory configuration
DMC_SDR_BA_EMRS EQU 2 ;
DMC_SDR_MEM_CASLAT EQU 3 ; Can use same value in SDRAM
DMC_SDR_CAS_LATENCY EQU (SDR_CASL<<1) ;6, 4'b0110; CASL:3,
DMC_SDR_t_DQSS EQU 0 ;
DMC_SDR_t_MRD EQU 2 ;
DMC_SDR_t_RAS EQU (((Startup_HCLK/1000*SDR_tRAS)-1)/1000000+1) ;7, Min 50ns
DMC_SDR_t_RC EQU (((Startup_HCLK/1000*SDR_tRC)-1)/1000000+1) ;10, Min 72.5ns
DMC_SDR_t_RCD EQU (((Startup_HCLK/1000*SDR_tRCD)-1)/1000000+1) ;4, Min 22.5ns
DMC_SDR_schedule_RCD EQU ((DMC_SDR_t_RCD - 3) << 3)
DMC_SDR_t_RFC EQU (((Startup_HCLK/1000*SDR_tRFC)-1)/1000000+1) ;11, Min 80ns
DMC_SDR_schedule_RFC EQU ((DMC_SDR_t_RFC - 3) << 5)
DMC_SDR_t_RP EQU (((Startup_HCLK/1000*SDR_tRP)-1)/1000000+1) ;4, Min 22.5ns
DMC_SDR_schedule_RP EQU ((DMC_SDR_t_RP - 3) << 3)
DMC_SDR_t_RRD EQU (((Startup_HCLK/1000*SDR_tRRD)-1)/1000000+1) ;3, Min 15ns
DMC_SDR_t_WR EQU 2 ;
DMC_SDR_t_WTR EQU 2 ;
DMC_SDR_t_XP EQU 2 ;
DMC_SDR_t_XSR EQU (((Startup_HCLK/1000*SDR_tXSR)-1)/1000000+1) ; Min 120ns
DMC_SDR_t_ESR EQU DMC_SDR_t_XSR ;
DMC_SDR_REFRESH_PRD EQU (((Startup_HCLK/1000*SDR_tREFRESH)-1)/1000000) ; 7.8us, 1040
;// mDDR memory configuration
DMC_DDR_BA_EMRS EQU 2 ;
DMC_DDR_MEM_CASLAT EQU 3 ;
DMC_DDR_CAS_LATENCY EQU (DDR_CASL<<1) ;6 Set Cas Latency to 3
DMC_DDR_t_DQSS EQU 1 ; Min 0.75 ~ 1.25
DMC_DDR_t_MRD EQU 2 ; Min 2 tck
DMC_DDR_t_RAS EQU (((Startup_HCLK/1000*DDR_tRAS)-1)/1000000+1) ;7, Min 45ns
DMC_DDR_t_RC EQU (((Startup_HCLK/1000*DDR_tRC)-1)/1000000+1) ;10, Min 67.5ns
DMC_DDR_t_RCD EQU (((Startup_HCLK/1000*DDR_tRCD)-1)/1000000+1) ;4,5(TRM), Min 22.5ns
DMC_DDR_schedule_RCD EQU ((DMC_DDR_t_RCD -3) <<3);
DMC_DDR_t_RFC EQU (((Startup_HCLK/1000*DDR_tRFC)-1)/1000000+1) ;11,18(TRM) Min 80ns
DMC_DDR_schedule_RFC EQU ((DMC_DDR_t_RFC -3) <<5);
DMC_DDR_t_RP EQU (((Startup_HCLK/1000*DDR_tRP)-1)/1000000+1) ;4, 5(TRM) Min 22.5ns
DMC_DDR_schedule_RP EQU ((DMC_DDR_t_RP -3) << 3);
DMC_DDR_t_RRD EQU (((Startup_HCLK/1000*DDR_tRRD)-1)/1000000+1) ;3, Min 15ns
DMC_DDR_t_WR EQU (((Startup_HCLK/1000*DDR_tWR)-1)/1000000+1) ; Min 15ns
DMC_DDR_t_WTR EQU 2 ;
DMC_DDR_t_XP EQU 2 ;1tck + tIS(1.5ns)
DMC_DDR_t_XSR EQU (((Startup_HCLK/1000*DDR_tXSR)-1)/1000000+1) ;17, Min 120ns
DMC_DDR_t_ESR EQU DMC_DDR_t_XSR ;
DMC_DDR_REFRESH_PRD EQU (((Startup_HCLK/1000*DDR_tREFRESH)-1)/1000000) ; TRM 2656
EXPORT InitDmc
AREA |C$$code|, CODE, READONLY
InitDmc PROC
[ DRAM = "DDR"
ldr r0, =DMC1_BASE ; DMC0 base address
ldr r1, =0x4
str r1, [r0, #INDEX_MEMCCMD] ; Enter the Config. Mode
ldr r1, =DMC_DDR_REFRESH_PRD ; Timing Para.
str r1, [r0, #INDEX_REFRESH]
ldr r1, =DMC_DDR_CAS_LATENCY
str r1, [r0, #INDEX_CASLAT]
ldr r1, =DMC_DDR_t_DQSS
str r1, [r0, #INDEX_T_DQSS]
ldr r1, =DMC_DDR_t_MRD
str r1, [r0, #INDEX_T_MRD]
ldr r1, =DMC_DDR_t_RAS
str r1, [r0, #INDEX_T_RAS]
ldr r1, =DMC_DDR_t_RC
str r1, [r0, #INDEX_T_RC]
ldr r1, =DMC_DDR_t_RCD
ldr r2, =DMC_DDR_schedule_RCD
orr r1, r1, r2
str r1, [r0, #INDEX_T_RCD]
ldr r1, =DMC_DDR_t_RFC
ldr r2, =DMC_DDR_schedule_RFC
orr r1, r1, r2
str r1, [r0, #INDEX_T_RFC]
ldr r1, =DMC_DDR_t_RP
ldr r2, =DMC_DDR_schedule_RP
orr r1, r1, r2
str r1, [r0, #INDEX_T_RP]
ldr r1, =DMC_DDR_t_RRD
str r1, [r0, #INDEX_T_RRD]
ldr r1, =DMC_DDR_t_WR
str r1, [r0, #INDEX_T_WR]
ldr r1, =DMC_DDR_t_WTR
str r1, [r0, #INDEX_T_WTR]
ldr r1, =DMC_DDR_t_XP
str r1, [r0, #INDEX_T_XP]
ldr r1, =DMC_DDR_t_XSR
str r1, [r0, #INDEX_T_XSR]
ldr r1, =DMC_DDR_t_ESR
str r1, [r0, #INDEX_T_ESR]
ldr r1, =DMC1_MEM_CFG
str r1, [r0, #INDEX_MEMCFG]
ldr r1, =DMC1_MEM_CFG2
str r1, [r0, #INDEX_MEMCFG2]
ldr r1, =DMC1_CHIP0_CFG
str r1, [r0, #INDEX_CHIP0_CFG]
ldr r1, =DMC1_USER_CFG
str r1, [r0, #INDEX_USER_CFG]
ldr r3, =rINFORM3
ldr r4, [r3];
ldr r3, =0xDEADDEAD
cmp r4, r3
beq WakeupFromSleep
;// Qos Service is not adapted
; DMC1 DDR Chip 0 configuration direct command reg
; NOP
ldr r1, =DMC_NOP0
str r1, [r0, #INDEX_DIRECTCMD]
; Precharge All
ldr r1, =DMC_PA0
str r1, [r0, #INDEX_DIRECTCMD]
; Auto Refresh 2 time
ldr r1, =DMC_AR0
str r1, [r0, #INDEX_DIRECTCMD]
str r1, [r0, #INDEX_DIRECTCMD]
; Mode Reg
ldr r1, =DMC_mDDR_MR0
str r1, [r0, #INDEX_DIRECTCMD]
; EMRS
ldr r1, =DMC_mDDR_EMR0 ; DS:Full, PASR:Full Array
str r1, [r0, #INDEX_DIRECTCMD]
; DMC1 DDR Chip 1 configuration direct command reg
; NOP
; ldr r1, =DMC_NOP1
; str r1, [r0, #INDEX_DMC_DIRECT_CMD]
; Precharge All
; ldr r1, =DMC_PA1
; str r1, [r0, #INDEX_DMC_DIRECT_CMD]
; Auto Refresh 2 time
; ldr r1, =DMC_AR1
; str r1, [r0, #INDEX_DMC_DIRECT_CMD]
; str r1, [r0, #INDEX_DMC_DIRECT_CMD]
; Mode Reg
; ldr r1, =DMC_DDR_MR1
; str r1, [r0, #INDEX_DMC_DIRECT_CMD]
WakeupFromSleep
; Enable DMC1
mov r1, #0x0
str r1, [r0, #INDEX_MEMCCMD]
Check_DMC1_READY
ldr r1, [r0, #INDEX_MEMSTAT]
mov r2, #0x3
and r1, r1, r2
cmp r1, #0x1
bne Check_DMC1_READY
NOP
cmp r4, r3
bne NORMAL
ldr r0, =0x50200000
mov pc, r0
]
NORMAL
mov pc, lr
; bx lr
ENDP
LTORG
END
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