option.inc

S3C6410 Startup Code,包括nand和onenand2种启动代码

;/*************************************************************************************
; 
;	Project Name : S3C6410 Validation
;
;	Copyright 2006 by Samsung Electronics, Inc.
;	All rights reserved.
;
;	Project Description :
;		This software is only for validating functions of the S3C6410.
;		Anybody can use this software without our permission.
;  
;--------------------------------------------------------------------------------------
; 
;	File Name : option.inc
;  
;	File Description : This file defines basic setting and configuration.
;
;	Author	: Haksoo,Kim
;	Dept. : AP Development Team
;	Created Date : 2006/11/08
;	Version : 0.1 
; 
;	History
;	- Created(Haksoo,Kim 2006/11/08)
; 	- Added PLL M,P,S Value (wonjoon.jang 2007/01/31) 
;*************************************************************************************/

					GBLL	SILICON
SILICON				SETL	{TRUE}

					GBLL	SYNCMODE
SYNCMODE			SETL	{TRUE}

					GBLL	ONE_ERROR
ONE_ERROR			SETL	{FALSE}
				
					GBLS	DMC
DMC					SETS	"DMC1"				
					
					GBLS	DRAM
DRAM				SETS	"DDR"									

 [ (DMC = "DMC0")
DRAM_BaseAddress	EQU		(0x40000000)
 ]
 [ (DMC = "DMC1")
DRAM_BaseAddress	EQU		(0x50000000)
 ] 

;top_of_stacks		EQU		(DRAM_BaseAddress+0x03ff8000)
;Exception_Vector	EQU		(DRAM_BaseAddress+0x03ffff00)
top_of_stacks		EQU		(DRAM_BaseAddress+0x07ff8000)
Exception_Vector	EQU		(DRAM_BaseAddress+0x07ffff00)

ONENAND_BaseAddress EQU		(0x70100000)
ONENAND_ReadBase	EQU		(0x01000000)	;6410 Base Map01 command, MEM_ADDR[25:24]
DownloadAddress		EQU		(DRAM_BaseAddress+0x00000000)

;; Clock Define
FIN					EQU		12000000

;==========================
;System Sync mode setting
;==========================
SYNC_HCLK			EQU		1

;=========================
;ARMCLK=666MHz, MPLL=266MHz,
;=========================
 [ ( 1 = 0)
 [ (SYNCMODE)
;VCO=1332MHz, Fout=1332MHz
APLL_MVAL		EQU	333
APLL_PVAL		EQU	3
APLL_SVAL		EQU	0
;VCO=1064MHz, Fout=266MHz
MPLL_MVAL		EQU	266
MPLL_PVAL		EQU	3
MPLL_SVAL		EQU	2

APLL_DIV		EQU	1
MPLL_DIV		EQU	1	;DOUT_MPLL = MPLL_Fout/2

HCLKx2_DIV		EQU	4	;HCLKx2 = APLL_Fout/4
HCLK_DIV		EQU	1	;AHB_CLK = HCLKx2/2
PCLK_DIV		EQU	3	;PCLK = HCLKx2/4
 |
;VCO=1332MHz, Fout=666MHz
APLL_MVAL		EQU	333
APLL_PVAL		EQU	3
APLL_SVAL		EQU	1
;VCO=1064MHz, Fout=266MHz
MPLL_MVAL		EQU	266
MPLL_PVAL		EQU	3
MPLL_SVAL		EQU	2

APLL_DIV		EQU	0
MPLL_DIV		EQU	1	;DOUT_MPLL = MPLL_Fout/2

HCLKx2_DIV		EQU	0	;HCLKx2 = MPLL_Fout
HCLK_DIV		EQU	1	;AHB_CLK = HCLKx2/2
PCLK_DIV		EQU	3	;PCLK = HCLKx2/4 
 ]
 ]

;=========================
;APLL=532MHz, MPLL=266MHz
;=========================
 [ ( 1 = 1)
;VCO=1064MHz, Fout=532MHz
APLL_MVAL		EQU	266
APLL_PVAL		EQU	3
APLL_SVAL		EQU	1
;VCO=1064MHz, Fout=266MHz
MPLL_MVAL		EQU	266
MPLL_PVAL		EQU	3
MPLL_SVAL		EQU	2

APLL_DIV		EQU	0
MPLL_DIV		EQU	1	;DOUT_MPLL = MPLL_Fout/2
HCLK_DIV		EQU	1	;AHB_CLK = HCLKx2/2
   [ (SYNC_HCLK = 1)
HCLKx2_DIV		EQU	1	;HCLKx2 = APLL_Fout/2
   |	; (ASYNC_HCLK = 1)
HCLKx2_DIV		EQU	0	;HCLKx2 = MPLL_Fout
   ]
PCLK_DIV		EQU	3	;PCLK = HCLKx2/4
 ]

;========================= 
;APLL=532MHz, MPLL=200MHz
;=========================
 [ ( 1 = 0)
;VCO=1064MHz, Fout=532MHz
APLL_MVAL		EQU	266
APLL_PVAL		EQU	3
APLL_SVAL		EQU	1
;VCO=1600MHz, Fout=200MHz
MPLL_MVAL		EQU	400
MPLL_PVAL		EQU	3
MPLL_SVAL		EQU	3

APLL_DIV		EQU	0
MPLL_DIV		EQU	1	;DOUT_MPLL = MPLL_Fout/2
HCLK_DIV		EQU	1	;AHB_CLK = HCLKx2/2
   [ (SYNC_HCLK = 1)
HCLKx2_DIV		EQU	1	;HCLKx2 = APLL_Fout/2
   |	; (ASYNC_HCLK = 1)
HCLKx2_DIV		EQU	0	;HCLKx2 = MPLL_Fout
   ]
PCLK_DIV		EQU	3	;PCLK = HCLKx2/4
 ]

;=========================
;APLL=400MHz, MPLL=266MHz
;=========================
 [ ( 1 = 0)
;VCO=1600MHz, Fout=400MHz
APLL_MVAL		EQU	400
APLL_PVAL		EQU	3
APLL_SVAL		EQU	2
;VCO=1064MHz, Fout=266MHz
MPLL_MVAL		EQU	266
MPLL_PVAL		EQU	3
MPLL_SVAL		EQU	2

APLL_DIV		EQU	0
MPLL_DIV		EQU	1	;DOUT_MPLL = MPLL_Fout/2
HCLK_DIV		EQU	1	;AHB_CLK = HCLKx2/2
   [ (SYNC_HCLK = 1)
HCLKx2_DIV		EQU	1	;HCLKx2 = APLL_Fout/2
   |	; (ASYNC_HCLK = 1)
HCLKx2_DIV		EQU	0	;HCLKx2 = MPLL_Fout
   ]
PCLK_DIV		EQU	3	;PCLK = HCLKx2/4
 ]

;=========================
;APLL=400MHz, MPLL=200MHz
;=========================
 [ ( 1 = 0)
;VCO=1600MHz, Fout=400MHz
APLL_MVAL		EQU	400
APLL_PVAL		EQU	3
APLL_SVAL		EQU	2
;VCO=1600MHz, Fout=200MHz
MPLL_MVAL		EQU	400
MPLL_PVAL		EQU	3	
MPLL_SVAL		EQU	3

APLL_DIV		EQU	0
MPLL_DIV		EQU	1	;DOUT_MPLL = MPLL_Fout/2
HCLK_DIV		EQU	1	;AHB_CLK = HCLKx2/2
   [ (SYNC_HCLK = 1)
HCLKx2_DIV		EQU	1	;HCLKx2 = APLL_Fout/2
   |	; (ASYNC_HCLK = 1)
HCLKx2_DIV		EQU	0	;HCLKx2 = MPLL_Fout
   ]
PCLK_DIV		EQU	3	;PCLK = HCLKx2/4
 ]
 
Startup_APLL		EQU	(((FIN>>APLL_SVAL)/APLL_PVAL)*APLL_MVAL)
Startup_MPLL		EQU	(((FIN>>MPLL_SVAL)/MPLL_PVAL)*MPLL_MVAL)
Startup_ARMCLK		EQU	(Startup_APLL/(APLL_DIV+1))

 [ (SYNC_HCLK = 1)
Startup_HCLK		EQU	(Startup_APLL/(HCLKx2_DIV+1)/(HCLK_DIV+1))
 |	; (ASYNC_HCLK = 1)
Startup_HCLK		EQU	(Startup_MPLL/(HCLKx2_DIV+1)/(HCLK_DIV+1))
 ]
Startup_PCLK		EQU	(Startup_HCLK/(PCLK_DIV+1))




				END