📄 top.tan.qmsg
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{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "inclk register top:inst\|dds:u2\|acc\[23\] register top:inst\|dds:u2\|acc\[23\] 1.039 ns " "Info: Minimum slack time is 1.039 ns for clock \"inclk\" between source register \"top:inst\|dds:u2\|acc\[23\]\" and destination register \"top:inst\|dds:u2\|acc\[23\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.830 ns + Shortest register register " "Info: + Shortest register to register delay is 0.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top:inst\|dds:u2\|acc\[23\] 1 REG LC_X15_Y7_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y7_N6; Fanout = 2; REG Node = 'top:inst\|dds:u2\|acc\[23\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.521 ns) + CELL(0.309 ns) 0.830 ns top:inst\|dds:u2\|acc\[23\] 2 REG LC_X15_Y7_N6 2 " "Info: 2: + IC(0.521 ns) + CELL(0.309 ns) = 0.830 ns; Loc. = LC_X15_Y7_N6; Fanout = 2; REG Node = 'top:inst\|dds:u2\|acc\[23\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.830 ns" { top:inst|dds:u2|acc[23] top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 37.23 % ) " "Info: Total cell delay = 0.309 ns ( 37.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.521 ns ( 62.77 % ) " "Info: Total interconnect delay = 0.521 ns ( 62.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.830 ns" { top:inst|dds:u2|acc[23] top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.830 ns" { top:inst|dds:u2|acc[23] top:inst|dds:u2|acc[23] } { 0.000ns 0.521ns } { 0.000ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination inclk 50.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"inclk\" is 50.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source inclk 50.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"inclk\" is 50.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 2.782 ns + Longest register " "Info: + Longest clock path from clock \"inclk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'inclk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 304 -16 152 320 "inclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns top:inst\|dds:u2\|acc\[23\] 2 REG LC_X15_Y7_N6 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y7_N6; Fanout = 2; REG Node = 'top:inst\|dds:u2\|acc\[23\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"inclk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'inclk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 304 -16 152 320 "inclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns top:inst\|dds:u2\|acc\[23\] 2 REG LC_X15_Y7_N6 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y7_N6; Fanout = 2; REG Node = 'top:inst\|dds:u2\|acc\[23\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.830 ns" { top:inst|dds:u2|acc[23] top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.830 ns" { top:inst|dds:u2|acc[23] top:inst|dds:u2|acc[23] } { 0.000ns 0.521ns } { 0.000ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[23] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "top:inst\|McuToFpga:u1\|Qtmp\[23\] en mcuclk 2.478 ns register " "Info: tsu for register \"top:inst\|McuToFpga:u1\|Qtmp\[23\]\" (data pin = \"en\", clock pin = \"mcuclk\") is 2.478 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.686 ns + Longest pin register " "Info: + Longest pin to register delay is 9.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 PIN PIN_4 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_4; Fanout = 24; PIN Node = 'en'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 248 424 592 264 "en" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.350 ns) + CELL(0.867 ns) 9.686 ns top:inst\|McuToFpga:u1\|Qtmp\[23\] 2 REG LC_X18_Y7_N5 2 " "Info: 2: + IC(7.350 ns) + CELL(0.867 ns) = 9.686 ns; Loc. = LC_X18_Y7_N5; Fanout = 2; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[23\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.217 ns" { en top:inst|McuToFpga:u1|Qtmp[23] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 24.12 % ) " "Info: Total cell delay = 2.336 ns ( 24.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.350 ns ( 75.88 % ) " "Info: Total interconnect delay = 7.350 ns ( 75.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.686 ns" { en top:inst|McuToFpga:u1|Qtmp[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.686 ns" { en en~out0 top:inst|McuToFpga:u1|Qtmp[23] } { 0.000ns 0.000ns 7.350ns } { 0.000ns 1.469ns 0.867ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mcuclk destination 7.245 ns - Shortest register " "Info: - Shortest clock path from clock \"mcuclk\" to destination register is 7.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mcuclk 1 CLK PIN_6 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 24; CLK Node = 'mcuclk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mcuclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 192 416 584 208 "mcuclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.065 ns) + CELL(0.711 ns) 7.245 ns top:inst\|McuToFpga:u1\|Qtmp\[23\] 2 REG LC_X18_Y7_N5 2 " "Info: 2: + IC(5.065 ns) + CELL(0.711 ns) = 7.245 ns; Loc. = LC_X18_Y7_N5; Fanout = 2; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[23\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.776 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[23] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 30.09 % ) " "Info: Total cell delay = 2.180 ns ( 30.09 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.065 ns ( 69.91 % ) " "Info: Total interconnect delay = 5.065 ns ( 69.91 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.245 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.245 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[23] } { 0.000ns 0.000ns 5.065ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.686 ns" { en top:inst|McuToFpga:u1|Qtmp[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.686 ns" { en en~out0 top:inst|McuToFpga:u1|Qtmp[23] } { 0.000ns 0.000ns 7.350ns } { 0.000ns 1.469ns 0.867ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.245 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.245 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[23] } { 0.000ns 0.000ns 5.065ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "mcuclk DAOUT\[0\] top:inst\|McuToFpga:u1\|Qtmp\[15\] 22.561 ns register " "Info: tco from clock \"mcuclk\" to destination pin \"DAOUT\[0\]\" through register \"top:inst\|McuToFpga:u1\|Qtmp\[15\]\" is 22.561 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mcuclk source 7.245 ns + Longest register " "Info: + Longest clock path from clock \"mcuclk\" to source register is 7.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mcuclk 1 CLK PIN_6 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 24; CLK Node = 'mcuclk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mcuclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 192 416 584 208 "mcuclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.065 ns) + CELL(0.711 ns) 7.245 ns top:inst\|McuToFpga:u1\|Qtmp\[15\] 2 REG LC_X18_Y7_N3 4 " "Info: 2: + IC(5.065 ns) + CELL(0.711 ns) = 7.245 ns; Loc. = LC_X18_Y7_N3; Fanout = 4; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[15\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.776 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[15] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 30.09 % ) " "Info: Total cell delay = 2.180 ns ( 30.09 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.065 ns ( 69.91 % ) " "Info: Total interconnect delay = 5.065 ns ( 69.91 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.245 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[15] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.245 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[15] } { 0.000ns 0.000ns 5.065ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.092 ns + Longest register pin " "Info: + Longest register to pin delay is 15.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top:inst\|McuToFpga:u1\|Qtmp\[15\] 1 REG LC_X18_Y7_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y7_N3; Fanout = 4; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[15\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|McuToFpga:u1|Qtmp[15] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.147 ns) + CELL(0.423 ns) 1.570 ns top:inst\|dds:u2\|address1\[0\]~181 2 COMB LC_X19_Y7_N0 2 " "Info: 2: + IC(1.147 ns) + CELL(0.423 ns) = 1.570 ns; Loc. = LC_X19_Y7_N0; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|address1\[0\]~181'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { top:inst|McuToFpga:u1|Qtmp[15] top:inst|dds:u2|address1[0]~181 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.648 ns top:inst\|dds:u2\|address1\[1\]~183 3 COMB LC_X19_Y7_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.648 ns; Loc. = LC_X19_Y7_N1; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|address1\[1\]~183'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { top:inst|dds:u2|address1[0]~181 top:inst|dds:u2|address1[1]~183 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.726 ns top:inst\|dds:u2\|address1\[2\]~185 4 COMB LC_X19_Y7_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.726 ns; Loc. = LC_X19_Y7_N2; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|address1\[2\]~185'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { top:inst|dds:u2|address1[1]~183 top:inst|dds:u2|address1[2]~185 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.804 ns top:inst\|dds:u2\|address1\[3\]~171 5 COMB LC_X19_Y7_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.804 ns; Loc. = LC_X19_Y7_N3; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|address1\[3\]~171'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { top:inst|dds:u2|address1[2]~185 top:inst|dds:u2|address1[3]~171 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.982 ns top:inst\|dds:u2\|address1\[4\]~173 6 COMB LC_X19_Y7_N4 4 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.982 ns; Loc. = LC_X19_Y7_N4; Fanout = 4; COMB Node = 'top:inst\|dds:u2\|address1\[4\]~173'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { top:inst|dds:u2|address1[3]~171 top:inst|dds:u2|address1[4]~173 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.603 ns top:inst\|dds:u2\|address1\[7\]~176 7 COMB LC_X19_Y7_N7 120 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.603 ns; Loc. = LC_X19_Y7_N7; Fanout = 120; COMB Node = 'top:inst\|dds:u2\|address1\[7\]~176'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.621 ns" { top:inst|dds:u2|address1[4]~173 top:inst|dds:u2|address1[7]~176 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.630 ns) + CELL(0.590 ns) 5.823 ns top:inst\|sinrom:u3\|Mux7~1364 8 COMB LC_X25_Y8_N1 1 " "Info: 8: + IC(2.630 ns) + CELL(0.590 ns) = 5.823 ns; Loc. = LC_X25_Y8_N1; Fanout = 1; COMB Node = 'top:inst\|sinrom:u3\|Mux7~1364'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.220 ns" { top:inst|dds:u2|address1[7]~176 top:inst|sinrom:u3|Mux7~1364 } "NODE_NAME" } } { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.209 ns) + CELL(0.442 ns) 7.474 ns top:inst\|sinrom:u3\|Mux7~1366 9 COMB LC_X25_Y7_N5 2 " "Info: 9: + IC(1.209 ns) + CELL(0.442 ns) = 7.474 ns; Loc. = LC_X25_Y7_N5; Fanout = 2; COMB Node = 'top:inst\|sinrom:u3\|Mux7~1366'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.651 ns" { top:inst|sinrom:u3|Mux7~1364 top:inst|sinrom:u3|Mux7~1366 } "NODE_NAME" } } { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.442 ns) 8.346 ns top:inst\|sinrom:u3\|Mux7~1372 10 COMB LC_X25_Y7_N1 1 " "Info: 10: + IC(0.430 ns) + CELL(0.442 ns) = 8.346 ns; Loc. = LC_X25_Y7_N1; Fanout = 1; COMB Node = 'top:inst\|sinrom:u3\|Mux7~1372'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.872 ns" { top:inst|sinrom:u3|Mux7~1366 top:inst|sinrom:u3|Mux7~1372 } "NODE_NAME" } } { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.114 ns) 8.887 ns top:inst\|sinrom:u3\|Mux7~1373 11 COMB LC_X25_Y7_N4 1 " "Info: 11: + IC(0.427 ns) + CELL(0.114 ns) = 8.887 ns; Loc. = LC_X25_Y7_N4; Fanout = 1; COMB Node = 'top:inst\|sinrom:u3\|Mux7~1373'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.541 ns" { top:inst|sinrom:u3|Mux7~1372 top:inst|sinrom:u3|Mux7~1373 } "NODE_NAME" } } { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.292 ns) 9.617 ns top:inst\|sinrom:u3\|Mux7~1367 12 COMB LC_X25_Y7_N0 1 " "Info: 12: + IC(0.438 ns) + CELL(0.292 ns) = 9.617 ns; Loc. = LC_X25_Y7_N0; Fanout = 1; COMB Node = 'top:inst\|sinrom:u3\|Mux7~1367'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.730 ns" { top:inst|sinrom:u3|Mux7~1373 top:inst|sinrom:u3|Mux7~1367 } "NODE_NAME" } } { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.442 ns) 10.482 ns top:inst\|sinrom:u3\|Mux7~1368 13 COMB LC_X25_Y7_N8 1 " "Info: 13: + IC(0.423 ns) + CELL(0.442 ns) = 10.482 ns; Loc. = LC_X25_Y7_N8; Fanout = 1; COMB Node = 'top:inst\|sinrom:u3\|Mux7~1368'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.865 ns" { top:inst|sinrom:u3|Mux7~1367 top:inst|sinrom:u3|Mux7~1368 } "NODE_NAME" } } { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 10.778 ns top:inst\|sinrom:u3\|Mux7~1369 14 COMB LC_X25_Y7_N9 1 " "Info: 14: + IC(0.182 ns) + CELL(0.114 ns) = 10.778 ns; Loc. = LC_X25_Y7_N9; Fanout = 1; COMB Node = 'top:inst\|sinrom:u3\|Mux7~1369'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { top:inst|sinrom:u3|Mux7~1368 top:inst|sinrom:u3|Mux7~1369 } "NODE_NAME" } } { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.190 ns) + CELL(2.124 ns) 15.092 ns DAOUT\[0\] 15 PIN PIN_108 0 " "Info: 15: + IC(2.190 ns) + CELL(2.124 ns) = 15.092 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'DAOUT\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.314 ns" { top:inst|sinrom:u3|Mux7~1369 DAOUT[0] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 312 832 1008 328 "DAOUT\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.016 ns ( 39.86 % ) " "Info: Total cell delay = 6.016 ns ( 39.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.076 ns ( 60.14 % ) " "Info: Total interconnect delay = 9.076 ns ( 60.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.092 ns" { top:inst|McuToFpga:u1|Qtmp[15] top:inst|dds:u2|address1[0]~181 top:inst|dds:u2|address1[1]~183 top:inst|dds:u2|address1[2]~185 top:inst|dds:u2|address1[3]~171 top:inst|dds:u2|address1[4]~173 top:inst|dds:u2|address1[7]~176 top:inst|sinrom:u3|Mux7~1364 top:inst|sinrom:u3|Mux7~1366 top:inst|sinrom:u3|Mux7~1372 top:inst|sinrom:u3|Mux7~1373 top:inst|sinrom:u3|Mux7~1367 top:inst|sinrom:u3|Mux7~1368 top:inst|sinrom:u3|Mux7~1369 DAOUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.092 ns" { top:inst|McuToFpga:u1|Qtmp[15] top:inst|dds:u2|address1[0]~181 top:inst|dds:u2|address1[1]~183 top:inst|dds:u2|address1[2]~185 top:inst|dds:u2|address1[3]~171 top:inst|dds:u2|address1[4]~173 top:inst|dds:u2|address1[7]~176 top:inst|sinrom:u3|Mux7~1364 top:inst|sinrom:u3|Mux7~1366 top:inst|sinrom:u3|Mux7~1372 top:inst|sinrom:u3|Mux7~1373 top:inst|sinrom:u3|Mux7~1367 top:inst|sinrom:u3|Mux7~1368 top:inst|sinrom:u3|Mux7~1369 DAOUT[0] } { 0.000ns 1.147ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.630ns 1.209ns 0.430ns 0.427ns 0.438ns 0.423ns 0.182ns 2.190ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.590ns 0.442ns 0.442ns 0.114ns 0.292ns 0.442ns 0.114ns 2.124ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.245 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[15] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.245 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[15] } { 0.000ns 0.000ns 5.065ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.092 ns" { top:inst|McuToFpga:u1|Qtmp[15] top:inst|dds:u2|address1[0]~181 top:inst|dds:u2|address1[1]~183 top:inst|dds:u2|address1[2]~185 top:inst|dds:u2|address1[3]~171 top:inst|dds:u2|address1[4]~173 top:inst|dds:u2|address1[7]~176 top:inst|sinrom:u3|Mux7~1364 top:inst|sinrom:u3|Mux7~1366 top:inst|sinrom:u3|Mux7~1372 top:inst|sinrom:u3|Mux7~1373 top:inst|sinrom:u3|Mux7~1367 top:inst|sinrom:u3|Mux7~1368 top:inst|sinrom:u3|Mux7~1369 DAOUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.092 ns" { top:inst|McuToFpga:u1|Qtmp[15] top:inst|dds:u2|address1[0]~181 top:inst|dds:u2|address1[1]~183 top:inst|dds:u2|address1[2]~185 top:inst|dds:u2|address1[3]~171 top:inst|dds:u2|address1[4]~173 top:inst|dds:u2|address1[7]~176 top:inst|sinrom:u3|Mux7~1364 top:inst|sinrom:u3|Mux7~1366 top:inst|sinrom:u3|Mux7~1372 top:inst|sinrom:u3|Mux7~1373 top:inst|sinrom:u3|Mux7~1367 top:inst|sinrom:u3|Mux7~1368 top:inst|sinrom:u3|Mux7~1369 DAOUT[0] } { 0.000ns 1.147ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.630ns 1.209ns 0.430ns 0.427ns 0.438ns 0.423ns 0.182ns 2.190ns } { 0.000ns 0.423ns 0.0⌨️ 快捷键说明
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