top.tan.qmsg

msp430驱动340*240程序 包括显示图片 文字 以及一些改变字体颜色功能等

{ "Info" "ITAN_NO_REG2REG_EXIST" "pll:inst1\|altpll:altpll_component\|_clk0 " "Info: No valid register-to-register data paths exist for clock \"pll:inst1\|altpll:altpll_component\|_clk0\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "inclk register top:inst\|dds:u2\|acc\[3\] register top:inst\|dds:u2\|acc\[22\] 46.899 ns " "Info: Slack time is 46.899 ns for clock \"inclk\" between source register \"top:inst\|dds:u2\|acc\[3\]\" and destination register \"top:inst\|dds:u2\|acc\[22\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.739 ns + Largest register register " "Info: + Largest register to register requirement is 49.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 50.000 ns " "Info: + Latch edge is 50.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination inclk 50.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"inclk\" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source inclk 50.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"inclk\" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"inclk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'inclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 304 -16 152 320 "inclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns top:inst\|dds:u2\|acc\[22\] 2 REG LC_X15_Y7_N5 6 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y7_N5; Fanout = 6; REG Node = 'top:inst\|dds:u2\|acc\[22\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { inclk top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[22] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"inclk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'inclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 304 -16 152 320 "inclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns top:inst\|dds:u2\|acc\[3\] 2 REG LC_X15_Y9_N6 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y9_N6; Fanout = 3; REG Node = 'top:inst\|dds:u2\|acc\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { inclk top:inst|dds:u2|acc[3] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[3] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[22] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[3] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[22] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[3] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.840 ns - Longest register register " "Info: - Longest register to register delay is 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top:inst\|dds:u2\|acc\[3\] 1 REG LC_X15_Y9_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y9_N6; Fanout = 3; REG Node = 'top:inst\|dds:u2\|acc\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|dds:u2|acc[3] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.575 ns) 1.103 ns top:inst\|dds:u2\|acc\[3\]~116COUT1_123 2 COMB LC_X15_Y9_N6 2 " "Info: 2: + IC(0.528 ns) + CELL(0.575 ns) = 1.103 ns; Loc. = LC_X15_Y9_N6; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[3\]~116COUT1_123'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.103 ns" { top:inst|dds:u2|acc[3] top:inst|dds:u2|acc[3]~116COUT1_123 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.183 ns top:inst\|dds:u2\|acc\[4\]~115COUT1_124 3 COMB LC_X15_Y9_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.183 ns; Loc. = LC_X15_Y9_N7; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[4\]~115COUT1_124'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { top:inst|dds:u2|acc[3]~116COUT1_123 top:inst|dds:u2|acc[4]~115COUT1_124 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.263 ns top:inst\|dds:u2\|acc\[5\]~114COUT1_125 4 COMB LC_X15_Y9_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.263 ns; Loc. = LC_X15_Y9_N8; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[5\]~114COUT1_125'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { top:inst|dds:u2|acc[4]~115COUT1_124 top:inst|dds:u2|acc[5]~114COUT1_125 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.521 ns top:inst\|dds:u2\|acc\[6\]~113 5 COMB LC_X15_Y9_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.521 ns; Loc. = LC_X15_Y9_N9; Fanout = 6; COMB Node = 'top:inst\|dds:u2\|acc\[6\]~113'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { top:inst|dds:u2|acc[5]~114COUT1_125 top:inst|dds:u2|acc[6]~113 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.657 ns top:inst\|dds:u2\|acc\[11\]~108 6 COMB LC_X15_Y8_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.657 ns; Loc. = LC_X15_Y8_N4; Fanout = 6; COMB Node = 'top:inst\|dds:u2\|acc\[11\]~108'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { top:inst|dds:u2|acc[6]~113 top:inst|dds:u2|acc[11]~108 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.865 ns top:inst\|dds:u2\|acc\[16\]~103 7 COMB LC_X15_Y8_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 1.865 ns; Loc. = LC_X15_Y8_N9; Fanout = 6; COMB Node = 'top:inst\|dds:u2\|acc\[16\]~103'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { top:inst|dds:u2|acc[11]~108 top:inst|dds:u2|acc[16]~103 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.001 ns top:inst\|dds:u2\|acc\[21\]~99 8 COMB LC_X15_Y7_N4 2 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 2.001 ns; Loc. = LC_X15_Y7_N4; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[21\]~99'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { top:inst|dds:u2|acc[16]~103 top:inst|dds:u2|acc[21]~99 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.840 ns top:inst\|dds:u2\|acc\[22\] 9 REG LC_X15_Y7_N5 6 " "Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 2.840 ns; Loc. = LC_X15_Y7_N5; Fanout = 6; REG Node = 'top:inst\|dds:u2\|acc\[22\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { top:inst|dds:u2|acc[21]~99 top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.312 ns ( 81.41 % ) " "Info: Total cell delay = 2.312 ns ( 81.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.528 ns ( 18.59 % ) " "Info: Total interconnect delay = 0.528 ns ( 18.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.840 ns" { top:inst|dds:u2|acc[3] top:inst|dds:u2|acc[3]~116COUT1_123 top:inst|dds:u2|acc[4]~115COUT1_124 top:inst|dds:u2|acc[5]~114COUT1_125 top:inst|dds:u2|acc[6]~113 top:inst|dds:u2|acc[11]~108 top:inst|dds:u2|acc[16]~103 top:inst|dds:u2|acc[21]~99 top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.840 ns" { top:inst|dds:u2|acc[3] top:inst|dds:u2|acc[3]~116COUT1_123 top:inst|dds:u2|acc[4]~115COUT1_124 top:inst|dds:u2|acc[5]~114COUT1_125 top:inst|dds:u2|acc[6]~113 top:inst|dds:u2|acc[11]~108 top:inst|dds:u2|acc[16]~103 top:inst|dds:u2|acc[21]~99 top:inst|dds:u2|acc[22] } { 0.000ns 0.528ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[22] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { inclk top:inst|dds:u2|acc[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { inclk inclk~out0 top:inst|dds:u2|acc[3] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.840 ns" { top:inst|dds:u2|acc[3] top:inst|dds:u2|acc[3]~116COUT1_123 top:inst|dds:u2|acc[4]~115COUT1_124 top:inst|dds:u2|acc[5]~114COUT1_125 top:inst|dds:u2|acc[6]~113 top:inst|dds:u2|acc[11]~108 top:inst|dds:u2|acc[16]~103 top:inst|dds:u2|acc[21]~99 top:inst|dds:u2|acc[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.840 ns" { top:inst|dds:u2|acc[3] top:inst|dds:u2|acc[3]~116COUT1_123 top:inst|dds:u2|acc[4]~115COUT1_124 top:inst|dds:u2|acc[5]~114COUT1_125 top:inst|dds:u2|acc[6]~113 top:inst|dds:u2|acc[11]~108 top:inst|dds:u2|acc[16]~103 top:inst|dds:u2|acc[21]~99 top:inst|dds:u2|acc[22] } { 0.000ns 0.528ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mcuclk register register top:inst\|McuToFpga:u1\|Qtmp\[4\] top:inst\|McuToFpga:u1\|Qtmp\[3\] 275.03 MHz Internal " "Info: Clock \"mcuclk\" Internal fmax is restricted to 275.03 MHz between source register \"top:inst\|McuToFpga:u1\|Qtmp\[4\]\" and destination register \"top:inst\|McuToFpga:u1\|Qtmp\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.830 ns + Longest register register " "Info: + Longest register to register delay is 1.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top:inst\|McuToFpga:u1\|Qtmp\[4\] 1 REG LC_X15_Y10_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y10_N0; Fanout = 4; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|McuToFpga:u1|Qtmp[4] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.715 ns) + CELL(0.115 ns) 1.830 ns top:inst\|McuToFpga:u1\|Qtmp\[3\] 2 REG LC_X12_Y9_N2 4 " "Info: 2: + IC(1.715 ns) + CELL(0.115 ns) = 1.830 ns; Loc. = LC_X12_Y9_N2; Fanout = 4; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.830 ns" { top:inst|McuToFpga:u1|Qtmp[4] top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 6.28 % ) " "Info: Total cell delay = 0.115 ns ( 6.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.715 ns ( 93.72 % ) " "Info: Total interconnect delay = 1.715 ns ( 93.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.830 ns" { top:inst|McuToFpga:u1|Qtmp[4] top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.830 ns" { top:inst|McuToFpga:u1|Qtmp[4] top:inst|McuToFpga:u1|Qtmp[3] } { 0.000ns 1.715ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.015 ns - Smallest " "Info: - Smallest clock skew is -0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mcuclk destination 7.230 ns + Shortest register " "Info: + Shortest clock path from clock \"mcuclk\" to destination register is 7.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mcuclk 1 CLK PIN_6 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 24; CLK Node = 'mcuclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mcuclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 192 416 584 208 "mcuclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.050 ns) + CELL(0.711 ns) 7.230 ns top:inst\|McuToFpga:u1\|Qtmp\[3\] 2 REG LC_X12_Y9_N2 4 " "Info: 2: + IC(5.050 ns) + CELL(0.711 ns) = 7.230 ns; Loc. = LC_X12_Y9_N2; Fanout = 4; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.761 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 30.15 % ) " "Info: Total cell delay = 2.180 ns ( 30.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.050 ns ( 69.85 % ) " "Info: Total interconnect delay = 5.050 ns ( 69.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[3] } { 0.000ns 0.000ns 5.050ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mcuclk source 7.245 ns - Longest register " "Info: - Longest clock path from clock \"mcuclk\" to source register is 7.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mcuclk 1 CLK PIN_6 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 24; CLK Node = 'mcuclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mcuclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 192 416 584 208 "mcuclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.065 ns) + CELL(0.711 ns) 7.245 ns top:inst\|McuToFpga:u1\|Qtmp\[4\] 2 REG LC_X15_Y10_N0 4 " "Info: 2: + IC(5.065 ns) + CELL(0.711 ns) = 7.245 ns; Loc. = LC_X15_Y10_N0; Fanout = 4; REG Node = 'top:inst\|McuToFpga:u1\|Qtmp\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.776 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[4] } "NODE_NAME" } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 30.09 % ) " "Info: Total cell delay = 2.180 ns ( 30.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.065 ns ( 69.91 % ) " "Info: Total interconnect delay = 5.065 ns ( 69.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.245 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.245 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[4] } { 0.000ns 0.000ns 5.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[3] } { 0.000ns 0.000ns 5.050ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.245 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.245 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[4] } { 0.000ns 0.000ns 5.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.830 ns" { top:inst|McuToFpga:u1|Qtmp[4] top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.830 ns" { top:inst|McuToFpga:u1|Qtmp[4] top:inst|McuToFpga:u1|Qtmp[3] } { 0.000ns 1.715ns } { 0.000ns 0.115ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[3] } { 0.000ns 0.000ns 5.050ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.245 ns" { mcuclk top:inst|McuToFpga:u1|Qtmp[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.245 ns" { mcuclk mcuclk~out0 top:inst|McuToFpga:u1|Qtmp[4] } { 0.000ns 0.000ns 5.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|McuToFpga:u1|Qtmp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { top:inst|McuToFpga:u1|Qtmp[3] } {  } {  } } } { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 21 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}