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msp430驱动340*240程序 包括显示图片 文字 以及一些改变字体颜色功能等

|Block1
daclk <= pll:inst1.c0
inclk => pll:inst1.inclk0
inclk => top:inst.TopClkDds
DAOUT[0] <= top:inst.TopData1[0]
DAOUT[1] <= top:inst.TopData1[1]
DAOUT[2] <= top:inst.TopData1[2]
DAOUT[3] <= top:inst.TopData1[3]
DAOUT[4] <= top:inst.TopData1[4]
DAOUT[5] <= top:inst.TopData1[5]
DAOUT[6] <= top:inst.TopData1[6]
DAOUT[7] <= top:inst.TopData1[7]
mcuclk => top:inst.TopClkMcu
data => top:inst.TopDada
en => top:inst.TopEn


|Block1|pll:inst1
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|Block1|pll:inst1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|top:inst
TopClkMcu => McuToFpga:u1.CLK
TopDada => McuToFpga:u1.DATA
TopEn => McuToFpga:u1.EN
TopClkDds => dds:u2.clk
TopData1[0] <= sinrom:u3.Data[0]
TopData1[1] <= sinrom:u3.Data[1]
TopData1[2] <= sinrom:u3.Data[2]
TopData1[3] <= sinrom:u3.Data[3]
TopData1[4] <= sinrom:u3.Data[4]
TopData1[5] <= sinrom:u3.Data[5]
TopData1[6] <= sinrom:u3.Data[6]
TopData1[7] <= sinrom:u3.Data[7]


|Block1|top:inst|McuToFpga:u1
CLK => Qtmp[0].CLK
CLK => Qtmp[1].CLK
CLK => Qtmp[2].CLK
CLK => Qtmp[3].CLK
CLK => Qtmp[4].CLK
CLK => Qtmp[5].CLK
CLK => Qtmp[6].CLK
CLK => Qtmp[7].CLK
CLK => Qtmp[8].CLK
CLK => Qtmp[9].CLK
CLK => Qtmp[10].CLK
CLK => Qtmp[11].CLK
CLK => Qtmp[12].CLK
CLK => Qtmp[13].CLK
CLK => Qtmp[14].CLK
CLK => Qtmp[15].CLK
CLK => Qtmp[16].CLK
CLK => Qtmp[17].CLK
CLK => Qtmp[18].CLK
CLK => Qtmp[19].CLK
CLK => Qtmp[20].CLK
CLK => Qtmp[21].CLK
CLK => Qtmp[22].CLK
CLK => Qtmp[23].CLK
DATA => Qtmp[23].DATAIN
EN => Qtmp[0].ENA
EN => Qtmp[1].ENA
EN => Qtmp[2].ENA
EN => Qtmp[3].ENA
EN => Qtmp[4].ENA
EN => Qtmp[5].ENA
EN => Qtmp[6].ENA
EN => Qtmp[7].ENA
EN => Qtmp[8].ENA
EN => Qtmp[9].ENA
EN => Qtmp[10].ENA
EN => Qtmp[11].ENA
EN => Qtmp[12].ENA
EN => Qtmp[13].ENA
EN => Qtmp[14].ENA
EN => Qtmp[15].ENA
EN => Qtmp[16].ENA
EN => Qtmp[17].ENA
EN => Qtmp[18].ENA
EN => Qtmp[19].ENA
EN => Qtmp[20].ENA
EN => Qtmp[21].ENA
EN => Qtmp[22].ENA
EN => Qtmp[23].ENA
frep[0] <= Qtmp[0].DB_MAX_OUTPUT_PORT_TYPE
frep[1] <= Qtmp[1].DB_MAX_OUTPUT_PORT_TYPE
frep[2] <= Qtmp[2].DB_MAX_OUTPUT_PORT_TYPE
frep[3] <= Qtmp[3].DB_MAX_OUTPUT_PORT_TYPE
frep[4] <= Qtmp[4].DB_MAX_OUTPUT_PORT_TYPE
frep[5] <= Qtmp[5].DB_MAX_OUTPUT_PORT_TYPE
frep[6] <= Qtmp[6].DB_MAX_OUTPUT_PORT_TYPE
frep[7] <= Qtmp[7].DB_MAX_OUTPUT_PORT_TYPE
frep[8] <= Qtmp[8].DB_MAX_OUTPUT_PORT_TYPE
frep[9] <= Qtmp[9].DB_MAX_OUTPUT_PORT_TYPE
frep[10] <= Qtmp[10].DB_MAX_OUTPUT_PORT_TYPE
frep[11] <= Qtmp[11].DB_MAX_OUTPUT_PORT_TYPE
frep[12] <= Qtmp[12].DB_MAX_OUTPUT_PORT_TYPE
frep[13] <= Qtmp[13].DB_MAX_OUTPUT_PORT_TYPE
frep[14] <= Qtmp[14].DB_MAX_OUTPUT_PORT_TYPE
phase[0] <= Qtmp[15].DB_MAX_OUTPUT_PORT_TYPE
phase[1] <= Qtmp[16].DB_MAX_OUTPUT_PORT_TYPE
phase[2] <= Qtmp[17].DB_MAX_OUTPUT_PORT_TYPE
phase[3] <= Qtmp[18].DB_MAX_OUTPUT_PORT_TYPE
phase[4] <= Qtmp[19].DB_MAX_OUTPUT_PORT_TYPE
phase[5] <= Qtmp[20].DB_MAX_OUTPUT_PORT_TYPE
phase[6] <= Qtmp[21].DB_MAX_OUTPUT_PORT_TYPE
phase[7] <= Qtmp[22].DB_MAX_OUTPUT_PORT_TYPE
phase[8] <= Qtmp[23].DB_MAX_OUTPUT_PORT_TYPE


|Block1|top:inst|dds:u2
frep[0] => Add0.IN24
frep[1] => Add0.IN23
frep[2] => Add0.IN22
frep[3] => Add0.IN21
frep[4] => Add0.IN20
frep[5] => Add0.IN19
frep[6] => Add0.IN18
frep[7] => Add0.IN17
frep[8] => Add0.IN16
frep[9] => Add0.IN15
frep[10] => Add0.IN14
frep[11] => Add0.IN13
frep[12] => Add0.IN12
frep[13] => Add0.IN11
frep[14] => Add0.IN10
phase[0] => Add1.IN9
phase[1] => Add1.IN8
phase[2] => Add1.IN7
phase[3] => Add1.IN6
phase[4] => Add1.IN5
phase[5] => Add1.IN4
phase[6] => Add1.IN3
phase[7] => Add1.IN2
phase[8] => Add1.IN1
clk => acc[0].CLK
clk => acc[1].CLK
clk => acc[2].CLK
clk => acc[3].CLK
clk => acc[4].CLK
clk => acc[5].CLK
clk => acc[6].CLK
clk => acc[7].CLK
clk => acc[8].CLK
clk => acc[9].CLK
clk => acc[10].CLK
clk => acc[11].CLK
clk => acc[12].CLK
clk => acc[13].CLK
clk => acc[14].CLK
clk => acc[15].CLK
clk => acc[16].CLK
clk => acc[17].CLK
clk => acc[18].CLK
clk => acc[19].CLK
clk => acc[20].CLK
clk => acc[21].CLK
clk => acc[22].CLK
clk => acc[23].CLK
address1[0] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[1] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[2] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[3] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[4] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[5] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[6] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[7] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
address1[8] <= Add1.DB_MAX_OUTPUT_PORT_TYPE


|Block1|top:inst|sinrom:u3
address[0] => Mux0.IN520
address[0] => Mux1.IN520
address[0] => Mux2.IN520
address[0] => Mux3.IN520
address[0] => Mux4.IN520
address[0] => Mux5.IN520
address[0] => Mux6.IN520
address[0] => Mux7.IN520
address[1] => Mux0.IN519
address[1] => Mux1.IN519
address[1] => Mux2.IN519
address[1] => Mux3.IN519
address[1] => Mux4.IN519
address[1] => Mux5.IN519
address[1] => Mux6.IN519
address[1] => Mux7.IN519
address[2] => Mux0.IN518
address[2] => Mux1.IN518
address[2] => Mux2.IN518
address[2] => Mux3.IN518
address[2] => Mux4.IN518
address[2] => Mux5.IN518
address[2] => Mux6.IN518
address[2] => Mux7.IN518
address[3] => Mux0.IN517
address[3] => Mux1.IN517
address[3] => Mux2.IN517
address[3] => Mux3.IN517
address[3] => Mux4.IN517
address[3] => Mux5.IN517
address[3] => Mux6.IN517
address[3] => Mux7.IN517
address[4] => Mux0.IN516
address[4] => Mux1.IN516
address[4] => Mux2.IN516
address[4] => Mux3.IN516
address[4] => Mux4.IN516
address[4] => Mux5.IN516
address[4] => Mux6.IN516
address[4] => Mux7.IN516
address[5] => Mux0.IN515
address[5] => Mux1.IN515
address[5] => Mux2.IN515
address[5] => Mux3.IN515
address[5] => Mux4.IN515
address[5] => Mux5.IN515
address[5] => Mux6.IN515
address[5] => Mux7.IN515
address[6] => Mux0.IN514
address[6] => Mux1.IN514
address[6] => Mux2.IN514
address[6] => Mux3.IN514
address[6] => Mux4.IN514
address[6] => Mux5.IN514
address[6] => Mux6.IN514
address[6] => Mux7.IN514
address[7] => Mux0.IN513
address[7] => Mux1.IN513
address[7] => Mux2.IN513
address[7] => Mux3.IN513
address[7] => Mux4.IN513
address[7] => Mux5.IN513
address[7] => Mux6.IN513
address[7] => Mux7.IN513
address[8] => Mux0.IN512
address[8] => Mux1.IN512
address[8] => Mux2.IN512
address[8] => Mux3.IN512
address[8] => Mux4.IN512
address[8] => Mux5.IN512
address[8] => Mux6.IN512
address[8] => Mux7.IN512
Data[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
Data[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
Data[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Data[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Data[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Data[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Data[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Data[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE