top.fit.qmsg

msp430驱动340*240程序 包括显示图片 文字 以及一些改变字体颜色功能等

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pll:inst1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pll:inst1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "pll.vhd" "" { Text "D:/xinhaoyuan/FPGA/pll.vhd" 127 -1 0 } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 336 200 440 496 "inst1" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.840 ns register register " "Info: Estimated most critical path is register to register delay of 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top:inst\|dds:u2\|acc\[2\] 1 REG LAB_X15_Y9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y9; Fanout = 3; REG Node = 'top:inst\|dds:u2\|acc\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|dds:u2|acc[2] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.575 ns) 1.036 ns top:inst\|dds:u2\|acc\[2\]~117COUT1_122 2 COMB LAB_X15_Y9 2 " "Info: 2: + IC(0.461 ns) + CELL(0.575 ns) = 1.036 ns; Loc. = LAB_X15_Y9; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[2\]~117COUT1_122'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.036 ns" { top:inst|dds:u2|acc[2] top:inst|dds:u2|acc[2]~117COUT1_122 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.116 ns top:inst\|dds:u2\|acc\[3\]~116COUT1_123 3 COMB LAB_X15_Y9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.116 ns; Loc. = LAB_X15_Y9; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[3\]~116COUT1_123'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { top:inst|dds:u2|acc[2]~117COUT1_122 top:inst|dds:u2|acc[3]~116COUT1_123 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.196 ns top:inst\|dds:u2\|acc\[4\]~115COUT1_124 4 COMB LAB_X15_Y9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.196 ns; Loc. = LAB_X15_Y9; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[4\]~115COUT1_124'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { top:inst|dds:u2|acc[3]~116COUT1_123 top:inst|dds:u2|acc[4]~115COUT1_124 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.276 ns top:inst\|dds:u2\|acc\[5\]~114COUT1_125 5 COMB LAB_X15_Y9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.276 ns; Loc. = LAB_X15_Y9; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[5\]~114COUT1_125'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { top:inst|dds:u2|acc[4]~115COUT1_124 top:inst|dds:u2|acc[5]~114COUT1_125 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.534 ns top:inst\|dds:u2\|acc\[6\]~113 6 COMB LAB_X15_Y9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.534 ns; Loc. = LAB_X15_Y9; Fanout = 6; COMB Node = 'top:inst\|dds:u2\|acc\[6\]~113'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { top:inst|dds:u2|acc[5]~114COUT1_125 top:inst|dds:u2|acc[6]~113 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.670 ns top:inst\|dds:u2\|acc\[11\]~108 7 COMB LAB_X15_Y8 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.670 ns; Loc. = LAB_X15_Y8; Fanout = 6; COMB Node = 'top:inst\|dds:u2\|acc\[11\]~108'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { top:inst|dds:u2|acc[6]~113 top:inst|dds:u2|acc[11]~108 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.806 ns top:inst\|dds:u2\|acc\[16\]~103 8 COMB LAB_X15_Y8 6 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.806 ns; Loc. = LAB_X15_Y8; Fanout = 6; COMB Node = 'top:inst\|dds:u2\|acc\[16\]~103'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { top:inst|dds:u2|acc[11]~108 top:inst|dds:u2|acc[16]~103 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.942 ns top:inst\|dds:u2\|acc\[21\]~99 9 COMB LAB_X15_Y7 2 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 1.942 ns; Loc. = LAB_X15_Y7; Fanout = 2; COMB Node = 'top:inst\|dds:u2\|acc\[21\]~99'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { top:inst|dds:u2|acc[16]~103 top:inst|dds:u2|acc[21]~99 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.840 ns top:inst\|dds:u2\|acc\[23\] 10 REG LAB_X15_Y7 2 " "Info: 10: + IC(0.000 ns) + CELL(0.898 ns) = 2.840 ns; Loc. = LAB_X15_Y7; Fanout = 2; REG Node = 'top:inst\|dds:u2\|acc\[23\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.898 ns" { top:inst|dds:u2|acc[21]~99 top:inst|dds:u2|acc[23] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.379 ns ( 83.77 % ) " "Info: Total cell delay = 2.379 ns ( 83.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns ( 16.23 % ) " "Info: Total interconnect delay = 0.461 ns ( 16.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.840 ns" { top:inst|dds:u2|acc[2] top:inst|dds:u2|acc[2]~117COUT1_122 top:inst|dds:u2|acc[3]~116COUT1_123 top:inst|dds:u2|acc[4]~115COUT1_124 top:inst|dds:u2|acc[5]~114COUT1_125 top:inst|dds:u2|acc[6]~113 top:inst|dds:u2|acc[11]~108 top:inst|dds:u2|acc[16]~103 top:inst|dds:u2|acc[21]~99 top:inst|dds:u2|acc[23] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 2 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 09 13:12:34 2008 " "Info: Processing ended: Tue Dec 09 13:12:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/xinhaoyuan/FPGA/top.fit.smsg " "Info: Generated suppressed messages file D:/xinhaoyuan/FPGA/top.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}