top.vhd

来自「msp430驱动340*240程序 包括显示图片 文字 以及一些改变字体颜色功能」· VHDL 代码 · 共 75 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity top is
	port(
		TopClkMcu:in std_logic;
		TopDada:in std_logic;
		TopEn:in std_logic;
		TopClkDds:in std_logic;
		TopData1: out integer range 0 to 255
		);
end top;  

architecture behav of top is
signal Topfrep:std_logic_vector(14 downto 0);
signal Topphase:std_logic_vector(8 downto 0);	
signal Topaddress1:std_logic_vector(8 downto 0);


component McuToFpga is	   
		port(
		CLK: in std_logic;				--同步时钟,上升研写入数据
		DATA: in std_logic;				--串行数据端口,先发低位然后高位
		EN: in std_logic;				--使能端,高电平开始传输,同步方式 
		frep: out std_logic_vector(14 downto 0);
		phase: out std_logic_vector(8 downto 0)
		);
end component ;	

component dds is	   
		port(
		frep:   in std_logic_vector(14 downto 0);
		phase:  in std_logic_vector(8 downto 0); 
		clk:	 in std_logic;
		address1:  out std_logic_vector(8 downto 0)
		);
end component ;	

component sinrom is	   
		port(
		 address:     in std_logic_vector(8 downto 0);	
		 Data:    out integer range 0 to 255
		);
end component ;	 

begin
	
	u1:	McuToFpga
	port map(
		clk=>TopClkMcu,				
		data=>TopDada,
		EN=>TopEn,
		frep=>Topfrep,			
		phase=>Topphase
		);	
		
	u2:	dds
	port map(
		frep=>Topfrep,
		phase=>Topphase, 
		clk=>TopClkDds,
		address1=>Topaddress1
		);
		
	u3:sinrom
	port map(
		 address=>Topaddress1,	
		 Data=>TopData1	
		 );	  
		 		 		
	
		 
   end;