c8051t610_defs.h

芯科原厂所有c8051fxx程序的例子。

// Address Definitions for bit-addressable SFRs
//-----------------------------------------------------------------------------

#define SFR_P0     0x80
#define SFR_TCON   0x88
#define SFR_P1     0x90
#define SFR_SCON0  0x98
#define SFR_P2     0xA0
#define SFR_IE     0xA8
#define SFR_P3     0xB0
#define SFR_IP     0xB8
#define SFR_SMB0CN 0xC0
#define SFR_TMR2CN 0xC8
#define SFR_PSW    0xD0
#define SFR_PCA0CN 0xD8
#define SFR_ACC    0xE0
#define SFR_ADC0CN 0xE8
#define SFR_B      0xF0
#define SFR_SPI0CN 0xF8


//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------

// TCON 0x88
SBIT (TF1, SFR_TCON, 7);               // Timer1 overflow flag
SBIT (TR1, SFR_TCON, 6);               // Timer1 on/off control
SBIT (TF0, SFR_TCON, 5);               // Timer0 overflow flag
SBIT (TR0, SFR_TCON, 4);               // Timer0 on/off control
SBIT (IE1, SFR_TCON, 3);               // Ext interrupt 1 edge flag
SBIT (IT1, SFR_TCON, 2);               // Ext interrupt 1 type
SBIT (IE0, SFR_TCON, 1);               // Ext interrupt 0 edge flag
SBIT (IT0, SFR_TCON, 0);               // Ext interrupt 0 type

// SCON0 0x98
SBIT (S0MODE, SFR_SCON0, 7);           // Serial mode control bit 0
                                       // Bit6 UNUSED
SBIT (MCE0, SFR_SCON0, 5);             // Multiprocessor communication enable
SBIT (REN0, SFR_SCON0, 4);             // Receive enable
SBIT (TB80, SFR_SCON0, 3);             // Transmit bit 8
SBIT (RB80, SFR_SCON0, 2);             // Receive bit 8
SBIT (TI0,  SFR_SCON0, 1);             // Transmit interrupt flag
SBIT (RI0,  SFR_SCON0, 0);             // Receive interrupt flag

// IE 0xA8
SBIT (EA,    SFR_IE, 7);               // Global interrupt enable
SBIT (ESPI0, SFR_IE, 6);               // SPI0 interrupt enable
SBIT (ET2,   SFR_IE, 5);               // Timer2 interrupt enable
SBIT (ES0,   SFR_IE, 4);               // UART0 interrupt enable
SBIT (ET1,   SFR_IE, 3);               // Timer1 interrupt enable
SBIT (EX1,   SFR_IE, 2);               // External interrupt 1 enable
SBIT (ET0,   SFR_IE, 1);               // Timer0 interrupt enable
SBIT (EX0,   SFR_IE, 0);               // External interrupt 0 enable

// IP 0xB8
                                       // Bit7 UNUSED
SBIT (PSPI0, SFR_IP, 6);               // SPI0 interrupt priority
SBIT (PT2,   SFR_IP, 5);               // Timer2 priority
SBIT (PS0,   SFR_IP, 4);               // UART0 priority
SBIT (PT1,   SFR_IP, 3);               // Timer1 priority
SBIT (PX1,   SFR_IP, 2);               // External interrupt 1 priority
SBIT (PT0,   SFR_IP, 1);               // Timer0 priority
SBIT (PX0,   SFR_IP, 0);               // External interrupt 0 priority

// SMB0CN 0xC0
SBIT (MASTER,  SFR_SMB0CN, 7);         // Master/slave indicator
SBIT (TXMODE,  SFR_SMB0CN, 6);         // Transmit mode indicator
SBIT (STA,     SFR_SMB0CN, 5);         // Start flag
SBIT (STO,     SFR_SMB0CN, 4);         // Stop flag
SBIT (ACKRQ,   SFR_SMB0CN, 3);         // Acknowledge request
SBIT (ARBLOST, SFR_SMB0CN, 2);         // Arbitration lost indicator
SBIT (ACK,     SFR_SMB0CN, 1);         // Acknowledge flag
SBIT (SI,      SFR_SMB0CN, 0);         // SMBus interrupt flag

// TMR2CN 0xC8
SBIT (TF2H,    SFR_TMR2CN, 7);         // Timer2 high byte overflow flag
SBIT (TF2L,    SFR_TMR2CN, 6);         // Timer2 low byte overflow flag
SBIT (TF2LEN,  SFR_TMR2CN, 5);         // Timer2 low byte interrupt enable
SBIT (T2CE,    SFR_TMR2CN, 4);         // Timer2 capture enable
SBIT (T2SPLIT, SFR_TMR2CN, 3);         // Timer2 split mode enable
SBIT (TR2,     SFR_TMR2CN, 2);         // Timer2 on/off control
SBIT (T2CSS,   SFR_TMR2CN, 1);         // Timer 2 Capture Source select
SBIT (T2XCLK,  SFR_TMR2CN, 0);         // Timer2 external clock select

// PSW 0xD0
SBIT (CY,  SFR_PSW, 7);                // Carry flag
SBIT (AC,  SFR_PSW, 6);                // Auxiliary carry flag
SBIT (F0,  SFR_PSW, 5);                // User flag 0
SBIT (RS1, SFR_PSW, 4);                // Register bank select 1
SBIT (RS0, SFR_PSW, 3);                // Register bank select 0
SBIT (OV,  SFR_PSW, 2);                // Overflow flag
SBIT (F1,  SFR_PSW, 1);                // User flag 1
SBIT (P,   SFR_PSW, 0);                // Accumulator parity flag

// PCA0CN 0xD8
SBIT (CF, SFR_PCA0CN, 7);              // PCA0 counter overflow flag
SBIT (CR, SFR_PCA0CN, 6);              // PCA0 counter run control
                                       // Bit5 UNUSED
SBIT (CCF4, SFR_PCA0CN, 4);            // PCA0 module4 capture/compare flag
SBIT (CCF3, SFR_PCA0CN, 3);            // PCA0 module3 capture/compare flag
SBIT (CCF2, SFR_PCA0CN, 2);            // PCA0 module2 capture/compare flag
SBIT (CCF1, SFR_PCA0CN, 1);            // PCA0 module1 capture/compare flag
SBIT (CCF0, SFR_PCA0CN, 0);            // PCA0 module0 capture/compare flag

// ADC0CN 0xE8
SBIT (AD0EN,   SFR_ADC0CN, 7);         // ADC0 enable
SBIT (AD0TM,   SFR_ADC0CN, 6);         // ADC0 track mode
SBIT (AD0INT,  SFR_ADC0CN, 5);         // ADC0 conversion complete interrupt flag
SBIT (AD0BUSY, SFR_ADC0CN, 4);         // ADC0 busy flag
SBIT (AD0WINT, SFR_ADC0CN, 3);         // ADC0 window compare interrupt flag
SBIT (AD0CM2,  SFR_ADC0CN, 2);         // ADC0 conversion mode select 2
SBIT (AD0CM1,  SFR_ADC0CN, 1);         // ADC0 conversion mode select 1
SBIT (AD0CM0,  SFR_ADC0CN, 0);         // ADC0 conversion mode select 0

// SPI0CN 0xF8
SBIT (SPIF,   SFR_SPI0CN, 7);          // SPI0 interrupt flag
SBIT (WCOL,   SFR_SPI0CN, 6);          // SPI0 write collision flag
SBIT (MODF,   SFR_SPI0CN, 5);          // SPI0 mode fault flag
SBIT (RXOVRN, SFR_SPI0CN, 4);          // SPI0 rx overrun flag
SBIT (NSSMD1, SFR_SPI0CN, 3);          // SPI0 slave select mode 1
SBIT (NSSMD0, SFR_SPI0CN, 2);          // SPI0 slave select mode 0
SBIT (TXBMT,  SFR_SPI0CN, 1);          // SPI0 transmit buffer empty
SBIT (SPIEN,  SFR_SPI0CN, 0);          // SPI0 SPI enable


//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------

#define INTERRUPT_INT0             0   // External Interrupt 0
#define INTERRUPT_TIMER0           1   // Timer0 Overflow
#define INTERRUPT_INT1             2   // External Interrupt 1
#define INTERRUPT_TIMER1           3   // Timer1 Overflow
#define INTERRUPT_UART0            4   // Serial Port 0
#define INTERRUPT_TIMER2           5   // Timer2 Overflow
#define INTERRUPT_SPI0             6   // Serial Peripheral Interface 0
#define INTERRUPT_SMBUS0           7   // SMBus0 Interface
                                       // Interrupt 8 is RESERVED
#define INTERRUPT_ADC0_WINDOW      9   // ADC0 Window Comparison
#define INTERRUPT_ADC0_EOC         10  // ADC0 End Of Conversion
#define INTERRUPT_PCA0             11  // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0      12  // Comparator0
#define INTERRUPT_COMPARATOR1      13  // Comparator1
#define INTERRUPT_TIMER3           14  // Timer3 Overflow

//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------

#endif                                 // #define C8051T610_DEFS_H

//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------