c8051f350_defs.h

芯科原厂所有c8051fxx程序的例子。

SFR16 (DP, 0x82);                         // Data Pointer

//-----------------------------------------------------------------------------
// Address Definitions for Bit-addressable Registers
//-----------------------------------------------------------------------------

#define SFR_P0       0x80
#define SFR_TCON     0x88
#define SFR_P1       0x90
#define SFR_SCON0    0x98
#define SFR_P2       0xA0
#define SFR_IE       0xA8
#define SFR_IP       0xB8
#define SFR_SMB0CN   0xC0
#define SFR_TMR2CN   0xC8
#define SFR_PSW      0xD0
#define SFR_PCA0CN   0xD8
#define SFR_ACC      0xE0
#define SFR_ADC0STA  0xE8
#define SFR_B        0xF0
#define SFR_SPI0CN   0xF8


//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------

// TCON 0x88
SBIT (TF1, SFR_TCON, 7);                  // TIMER 1 OVERFLOW FLAG
SBIT (TR1, SFR_TCON, 6);                  // TIMER 1 ON/OFF CONTROL
SBIT (TF0, SFR_TCON, 5);                  // TIMER 0 OVERFLOW FLAG
SBIT (TR0, SFR_TCON, 4);                  // TIMER 0 ON/OFF CONTROL
SBIT (IE1, SFR_TCON, 3);                  // EXT. INTERRUPT 1 EDGE FLAG
SBIT (IT1, SFR_TCON, 2);                  // EXT. INTERRUPT 1 TYPE
SBIT (IE0, SFR_TCON, 1);                  // EXT. INTERRUPT 0 EDGE FLAG
SBIT (IT0, SFR_TCON, 0);                  // EXT. INTERRUPT 0 TYPE

// SCON0 0x98
SBIT (S0MODE, SFR_SCON0, 7);              // UART 0 MODE
                                          // bit 6 not used
SBIT (MCE0, SFR_SCON0, 5);                // UART 0 MCE
SBIT (REN0, SFR_SCON0, 4);                // UART 0 RX ENABLE
SBIT (TB80, SFR_SCON0, 3);                // UART 0 TX BIT 8
SBIT (RB80, SFR_SCON0, 2);                // UART 0 RX BIT 8
SBIT (TI0, SFR_SCON0, 1);                 // UART 0 TX INTERRUPT FLAG
SBIT (RI0, SFR_SCON0, 0);                 // UART 0 RX INTERRUPT FLAG

// IE 0xA8
SBIT (EA, SFR_IE, 7);                     // GLOBAL INTERRUPT ENABLE
SBIT (ESPI0, SFR_IE, 6);                  // SPI0 INTERRUPT ENABLE
SBIT (ET2, SFR_IE, 5);                    // TIMER 2 INTERRUPT ENABLE
SBIT (ES0, SFR_IE, 4);                    // UART0 INTERRUPT ENABLE
SBIT (ET1, SFR_IE, 3);                    // TIMER 1 INTERRUPT ENABLE
SBIT (EX1, SFR_IE, 2);                    // EXTERNAL INTERRUPT 1 ENABLE
SBIT (ET0, SFR_IE, 1);                    // TIMER 0 INTERRUPT ENABLE
SBIT (EX0, SFR_IE, 0);                    // EXTERNAL INTERRUPT 0 ENABLE

// IP 0xB8
                                          // bit 7 not used
SBIT (PSPI0, SFR_IP, 6);                  // SPI0 PRIORITY
SBIT (PT2, SFR_IP, 5);                    // TIMER 2 PRIORITY
SBIT (PS0, SFR_IP, 4);                    // UART0 PRIORITY
SBIT (PT1, SFR_IP, 3);                    // TIMER 1 PRIORITY
SBIT (PX1, SFR_IP, 2);                    // EXTERNAL INTERRUPT 1 PRIORITY
SBIT (PT0, SFR_IP, 1);                    // TIMER 0 PRIORITY
SBIT (PX0, SFR_IP, 0);                    // EXTERNAL INTERRUPT 0 PRIORITY

// SMB0CN 0xC0
SBIT (MASTER, SFR_SMB0CN, 7);             // SMBUS 0 MASTER/SLAVE
SBIT (TXMODE, SFR_SMB0CN, 6);             // SMBUS 0 TRANSMIT MODE
SBIT (STA, SFR_SMB0CN, 5);                // SMBUS 0 START FLAG
SBIT (STO, SFR_SMB0CN, 4);                // SMBUS 0 STOP FLAG
SBIT (ACKRQ, SFR_SMB0CN, 3);              // SMBUS 0 ACKNOWLEDGE REQUEST
SBIT (ARBLOST, SFR_SMB0CN, 2);            // SMBUS 0 ARBITRATION LOST
SBIT (ACK, SFR_SMB0CN, 1);                // SMBUS 0 ACKNOWLEDGE FLAG
SBIT (SI, SFR_SMB0CN, 0);                 // SMBUS 0 INTERRUPT PENDING FLAG

// TMR2CN 0xC8
SBIT (TF2H, SFR_TMR2CN, 7);               // TIMER 2 HIGH BYTE OVERFLOW FLAG
SBIT (TF2L, SFR_TMR2CN, 6);               // TIMER 2 LOW BYTE OVERFLOW FLAG
SBIT (TF2LEN, SFR_TMR2CN, 5);             // TIMER 2 LOW BYTE INTERRUPT ENABLE
                                          // bit 4 not used
SBIT (T2SPLIT, SFR_TMR2CN, 3);            // TIMER 2 SPLIT MODE ENABLE
SBIT (TR2, SFR_TMR2CN, 2);                // TIMER 2 ON/OFF CONTROL
                                          // bit 1 not used
SBIT (T2XCLK, SFR_TMR2CN, 0);             // TIMER 2 EXTERNAL CLOCK SELECT

// PSW 0xD0
SBIT(CY, SFR_PSW, 7);                     // CARRY FLAG
SBIT(AC, SFR_PSW, 6);                     // AUXILIARY CARRY FLAG
SBIT(F0, SFR_PSW, 5);                     // USER FLAG 0
SBIT(RS1, SFR_PSW, 4);                    // REGISTER BANK SELECT 1
SBIT(RS0, SFR_PSW, 3);                    // REGISTER BANK SELECT 0
SBIT(OV, SFR_PSW, 2);                     // OVERFLOW FLAG
SBIT(F1, SFR_PSW, 1);                     // USER FLAG 1
SBIT(P, SFR_PSW, 0);                      // ACCUMULATOR PARITY FLAG

// PCA0CN 0xD8
SBIT (CF, SFR_PCA0CN, 7);                 // PCA 0 COUNTER OVERFLOW FLAG
SBIT (CR, SFR_PCA0CN, 6);                 // PCA 0 COUNTER RUN CONTROL BIT
                                          // bit 5 not used
                                          // bit 4 not used
                                          // bit 3 not used
SBIT (CCF2, SFR_PCA0CN, 2);               // PCA 0 MODULE 2 INTERRUPT FLAG
SBIT (CCF1, SFR_PCA0CN, 1);               // PCA 0 MODULE 1 INTERRUPT FLAG
SBIT (CCF0, SFR_PCA0CN, 0);               // PCA 0 MODULE 0 INTERRUPT FLAG

// ADC0STA 0xE8
SBIT (AD0BUSY, SFR_ADC0STA, 7);           // ADC 0 CONVERSION IN PROGRESS FLAG
SBIT (AD0CBSY, SFR_ADC0STA, 6);           // ADC 0 CALIBRATION IN PROGRESS FLAG
SBIT (AD0INT, SFR_ADC0STA, 5);            // ADC 0 CONVERSION COMPLETE FLAG
SBIT (AD0S3C, SFR_ADC0STA, 4);            // ADC 0 SINC3 FILTER ERROR FLAG
SBIT (AD0FFC, SFR_ADC0STA, 3);            // ADC 0 FAST FILTER ERROR FLAG
SBIT (AD0CALC, SFR_ADC0STA, 2);           // ADC 0 CALIBRATION COMPLETE FLAG
SBIT (AD0ERR, SFR_ADC0STA, 1);            // ADC 0 ERROR FLAG
SBIT (AD0OVR, SFR_ADC0STA, 0);            // ADC 0 OVERRUN FLAG

// SPI0CN 0xF8
SBIT (SPIF, SFR_SPI0CN, 7);               // SPI 0 INTERRUPT FLAG
SBIT (WCOL, SFR_SPI0CN, 6);               // SPI 0 WRITE COLLISION FLAG
SBIT (MODF, SFR_SPI0CN, 5);               // SPI 0 MODE FAULT FLAG
SBIT (RXOVRN, SFR_SPI0CN, 4);             // SPI 0 RX OVERRUN FLAG
SBIT (NSSMD1, SFR_SPI0CN, 3);             // SPI 0 SLAVE SELECT MODE 1
SBIT (NSSMD0, SFR_SPI0CN, 2);             // SPI 0 SLAVE SELECT MODE 0
SBIT (TXBMT, SFR_SPI0CN, 1);              // SPI 0 TX BUFFER EMPTY FLAG
SBIT (SPIEN, SFR_SPI0CN, 0);              // SPI 0 SPI ENABLE

//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------

#define INTERRUPT_INT0                 0  // External Interrupt 0
#define INTERRUPT_TIMER0               1  // Timer0 Overflow
#define INTERRUPT_INT1                 2  // External Interrupt 1
#define INTERRUPT_TIMER1               3  // Timer1 Overflow
#define INTERRUPT_UART0                4  // Serial Port 0
#define INTERRUPT_TIMER2               5  // Timer2 Overflow
#define INTERRUPT_SPI0                 6  // Serial Peripheral Interface 0
#define INTERRUPT_SMB0                 7  // SMB0 Interrupt
                                          // 8 reserved
                                          // 9 reserved
#define INTERRUPT_ADC0                10  // ADC0 Interrupt
#define INTERRUPT_PCA0                11  // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0         12  // Comparator
                                          // 13 reserved
#define INTERRUPT_TIMER3              14  // Timer3 Overflow

//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------

#endif                                    // #define C8051F350_DEFS_H

//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------