c8051f360.h

芯科原厂所有c8051fxx程序的例子。

sfr P0MASK          = 0xF4;            // Port 0 mask
sfr P3MDIN          = 0xF4;            // Port 3 input mode configuration
sfr PCA0CPL5        = 0xF5;            // PCA0 module 5 capture low
sfr PCA0CPH5        = 0xF6;            // PCA0 module 5 capture high
sfr EMI0TC          = 0xF7;            // EMIF timing control
sfr SPI0CN          = 0xF8;            // SPI0 control
sfr PCA0L           = 0xF9;            // PCA0 counter low
sfr PCA0H           = 0xFA;            // PCA0 counter high
sfr PCA0CPL0        = 0xFB;            // PCA0 module 0 capture low
sfr PCA0CPH0        = 0xFC;            // PCA0 module 0 capture high
sfr PCA0CPL4        = 0xFD;            // PCA0 module 4 capture low
sfr PCA0CPH4        = 0xFE;            // PCA0 module 4 capture high
sfr VDM0CN          = 0xFF;            // VDD monitor control

//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------

// TCON 0x88
sbit TF1       = 0x8F;                 // Timer 1 overflow flag
sbit TR1       = 0x8E;                 // Timer 1 on/off control
sbit TF0       = 0x8D;                 // Timer 0 overflow flag
sbit TR0       = 0x8C;                 // Timer 0 on/off control
sbit IE1       = 0x8B;                 // Ext. Interrupt 1 edge flag
sbit IT1       = 0x8A;                 // Ext. Interrupt 1 type
sbit IE0       = 0x89;                 // Ext. Interrupt 0 edge flag
sbit IT0       = 0x88;                 // Ext. Interrupt 0 type

// SCON0 0x98
sbit S0MODE    = 0x9F;                 // UART0 mode
                                       // Bit 6 Unused
sbit MCE0      = 0x9D;                 // UART0 mce
sbit REN0      = 0x9C;                 // UART0 RX enable
sbit TB80      = 0x9B;                 // UART0 TX bit 8
sbit RB80      = 0x9A;                 // UART0 RX bit 8
sbit TI0       = 0x99;                 // UART0 TX interrupt flag
sbit RI0       = 0x98;                 // UART0 RX interrupt flag

// IE 0xA8
sbit EA        = 0xAF;                 // Global interrupt enable
sbit ESPI0     = 0xAE;                 // SPI0 interrupt enable
sbit ET2       = 0xAD;                 // Timer 2 interrupt enable
sbit ES0       = 0xAC;                 // UART0 interrupt enable
sbit ET1       = 0xAB;                 // Timer 1 interrupt enable
sbit EX1       = 0xAA;                 // External interrupt 1 enable
sbit ET0       = 0xA9;                 // Timer 0 interrupt enable
sbit EX0       = 0xA8;                 // External interrupt 0 enable

// IP 0xB8
                                       // Bit 7 Unused
sbit PSPI0     = 0xBE;                 // SPI0 priority
sbit PT2       = 0xBD;                 // Timer 2 priority
sbit PS0       = 0xBC;                 // UART0 priority
sbit PT1       = 0xBB;                 // Timer 1 priority
sbit PX1       = 0xBA;                 // External interrupt 1 priority
sbit PT0       = 0xB9;                 // Timer 0 priority
sbit PX0       = 0xB8;                 // External interrupt 0 priority

// SMB0CN 0xC0
sbit MASTER    = 0xC7;                 // SMBus0 master/slave
sbit TXMODE    = 0xC6;                 // SMBus0 transmit mode
sbit STA       = 0xC5;                 // SMBus0 start flag
sbit STO       = 0xC4;                 // SMBus0 stop flag
sbit ACKRQ     = 0xC3;                 // SMBus0 acknowledge request
sbit ARBLOST   = 0xC2;                 // SMBus0 arbitration lost
sbit ACK       = 0xC1;                 // SMBus0 acknowledge flag
sbit SI        = 0xC0;                 // SMBus0 interrupt pending flag

// TMR2CN 0xC8
sbit TF2H      = 0xCF;                 // Timer 2 high byte overflow flag
sbit TF2L      = 0xCE;                 // Timer 2 low byte overflow flag
sbit TF2LEN    = 0xCD;                 // Timer 2 low byte interrupt enable
sbit TF2CEN    = 0xCC;                 // Timer 2 capture enable
sbit T2SPLIT   = 0xCB;                 // Timer 2 split mode enable
sbit TR2       = 0xCA;                 // Timer 2 on/off control
                                       // Bit 1 Unused
sbit T2XCLK    = 0xC8;                 // Timer 2 external clock select

// PSW 0xD0
sbit CY        = 0xD7;                 // Carry flag
sbit AC        = 0xD6;                 // Auxiliary carry flag
sbit F0        = 0xD5;                 // User flag 0
sbit RS1       = 0xD4;                 // Register bank select 1
sbit RS0       = 0xD3;                 // Register bank select 0
sbit OV        = 0xD2;                 // Overflow flag
sbit F1        = 0xD1;                 // User flag 1
sbit P         = 0xD0;                 // Accumulator parity flag

// PCA0CN 0xD8
sbit CF        = 0xDF;                 // PCA0 counter overflow flag
sbit CR        = 0xDE;                 // PCA0 counter run control bit
sbit CCF5      = 0xDD;                 // PCA0 module 5 interrupt flag
sbit CCF4      = 0xDC;                 // PCA0 module 4 interrupt flag
sbit CCF3      = 0xDB;                 // PCA0 module 3 interrupt flag
sbit CCF2      = 0xDA;                 // PCA0 module 2 interrupt flag
sbit CCF1      = 0xD9;                 // PCA0 module 1 interrupt flag
sbit CCF0      = 0xD8;                 // PCA0 module 0 interrupt flag

// ADC0CN 0xE8
sbit AD0EN     = 0xEF;                 // ADC0 enable
sbit AD0TM     = 0xEE;                 // ADC0 track mode
sbit AD0INT    = 0xED;                 // ADC0 conv. complete interrupt flag
sbit AD0BUSY   = 0xEC;                 // ADC0 busy flag
sbit AD0WINT   = 0xEB;                 // ADC0 window compare interrupt flag
sbit AD0CM2    = 0xEA;                 // ADC0 conversion mode select 2
sbit AD0CM1    = 0xE9;                 // ADC0 conversion mode select 1
sbit AD0CM0    = 0xE8;                 // ADC0 conversion mode select 0

// SPI0CN 0xF8
sbit SPIF      = 0xFF;                 // SPI0 interrupt flag
sbit WCOL      = 0xFE;                 // SPI0 write collision flag
sbit MODF      = 0xFD;                 // SPI0 mode fault flag
sbit RXOVRN    = 0xFC;                 // SPI0 RX overrun flag
sbit NSSMD1    = 0xFB;                 // SPI0 slave select mode 1
sbit NSSMD0    = 0xFA;                 // SPI0 slave select mode 0
sbit TXBMT     = 0xF9;                 // SPI0 TX buffer empty flag
sbit SPIEN     = 0xF8;                 // SPI0 SPI0 enable

//-----------------------------------------------------------------------------
// SFR Page Definitions
//-----------------------------------------------------------------------------

#define CONFIG_PAGE       0x0F         // SYSTEM AND PORT CONFIGURATION PAGE
#define LEGACY_PAGE       0x00         // LEGACY SFR PAGE
#define TIMER01_PAGE      0x00         // TIMER 0 AND TIMER 1
#define CPT0_PAGE         0x00         // COMPARATOR 0
#define CPT1_PAGE         0x00         // COMPARATOR 1
#define UART0_PAGE        0x00         // UART 0
#define SPI0_PAGE         0x00         // SPI 0
#define EMI0_PAGE         0x0F         // EXTERNAL MEMORY INTERFACE
#define ADC0_PAGE         0x00         // ADC 0
#define SMB0_PAGE         0x00         // SMBUS 0
#define TMR2_PAGE         0x00         // TIMER 2
#define TMR3_PAGE         0x00         // TIMER 3
#define DAC0_PAGE         0x00         // DAC 0
#define PCA0_PAGE         0x00         // PCA 0
#define PLL0_PAGE         0x0F         // PLL 0
#define MAC0_PAGE         0x00         // MAC 0
#define MATCH_PAGE        0x00         // PORT0, PORT1, PORT2 MATCH

//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------

#define INTERRUPT_INT0             0   // External Interrupt 0
#define INTERRUPT_TIMER0           1   // Timer0 Overflow
#define INTERRUPT_INT1             2   // External Interrupt 1
#define INTERRUPT_TIMER1           3   // Timer1 Overflow
#define INTERRUPT_UART0            4   // Serial Port 0
#define INTERRUPT_TIMER2           5   // Timer2 Overflow
#define INTERRUPT_SPI0             6   // Serial Peripheral Interface 0
#define INTERRUPT_SMBUS0           7   // SMBus0 Interface
#define INTERRUPT_ADC0_WINDOW      9   // ADC0 Window Comparison
#define INTERRUPT_ADC0_EOC         10  // ADC0 End Of Conversion
#define INTERRUPT_PCA0             11  // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0      12  // Comparator0
#define INTERRUPT_COMPARATOR1      13  // Comparator1
#define INTERRUPT_TIMER3           14  // Timer3 Overflow
#define INTERRUPT_PORT_MATCH       16  // Port Match

//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------

#endif                                 // #define C8051F360_H

//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------