📄 c8051f360_defs.h
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SFR16 (MAC0RND, 0xAE); // MAC0 Round
SFR16 (ADC0, 0xBD); // ADC0 Data
SFR16 (ADC0GT, 0xC3); // ADC0 Greater-Than Compare
SFR16 (ADC0LT, 0xC5); // ADC0 Less-Than Compare
SFR16 (TMR2RL, 0xCA); // Timer 2 Reload
SFR16 (TMR2, 0xCC); // Timer 2 Counter
SFR16 (MAC0ACCL, 0xD2); // MAC0 Accumulator Low
SFR16 (MAC0ACCH, 0xD4); // MAC0 Accumulator High
SFR16 (PCA0CP1, 0xE9); // PCA0 Module 1 Capture/Compare
SFR16 (PCA0CP2, 0xEB); // PCA0 Module 2 Capture/Compare
SFR16 (PCA0CP3, 0xED); // PCA0 Module 3 Capture/Compare
SFR16 (MAC0B, 0xF1); // MAC0 B Operand
SFR16 (PCA0CP5, 0xF5); // PCA0 Module 5 Capture/Compare
SFR16 (PCA0, 0xF9); // PCA0 Counter
SFR16 (PCA0CP0, 0xFB); // PCA0 Module 0 Capture/Compare
SFR16 (PCA0CP4, 0xFD); // PCA0 Module 4 Capture/Compare
//-----------------------------------------------------------------------------
// Address Definitions for Bit-addressable Registers
//-----------------------------------------------------------------------------
#define SFR_P0 0x80
#define SFR_TCON 0x88
#define SFR_P1 0x90
#define SFR_SCON0 0x98
#define SFR_P2 0xA0
#define SFR_IE 0xA8
#define SFR_P3 0xB0
#define SFR_IP 0xB8
#define SFR_SMB0CN 0xC0
#define SFR_TMR2CN 0xC8
#define SFR_PSW 0xD0
#define SFR_PCA0CN 0xD8
#define SFR_ACC 0xE0
#define SFR_ADC0CN 0xE8
#define SFR_B 0xF0
#define SFR_SPI0CN 0xF8
//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------
// TCON 0x88
SBIT (TF1, SFR_TCON, 7); // Timer 1 Overflow Flag
SBIT (TR1, SFR_TCON, 6); // Timer 1 On/Off Control
SBIT (TF0, SFR_TCON, 5); // Timer 0 Overflow Flag
SBIT (TR0, SFR_TCON, 4); // Timer 0 On/Off Control
SBIT (IE1, SFR_TCON, 3); // Ext. Interrupt 1 Edge Flag
SBIT (IT1, SFR_TCON, 2); // Ext. Interrupt 1 Type
SBIT (IE0, SFR_TCON, 1); // Ext. Interrupt 0 Edge Flag
SBIT (IT0, SFR_TCON, 0); // Ext. Interrupt 0 Type
// SCON0 0x98
SBIT (S0MODE, SFR_SCON0, 7); // UART0 Mode
// Bit6 UNUSED
SBIT (MCE0, SFR_SCON0, 5); // UART0 MCE
SBIT (REN0, SFR_SCON0, 4); // UART0 RX Enable
SBIT (TB80, SFR_SCON0, 3); // UART0 TX Bit 8
SBIT (RB80, SFR_SCON0, 2); // UART0 RX Bit 8
SBIT (TI0, SFR_SCON0, 1); // UART0 TX Interrupt Flag
SBIT (RI0, SFR_SCON0, 0); // UART0 RX Interrupt Flag
// IE 0xA8
SBIT (EA, SFR_IE, 7); // Global Interrupt Enable
SBIT (ESPI0, SFR_IE, 6); // SPI0 Interrupt Enable
SBIT (ET2, SFR_IE, 5); // Timer 2 Interrupt Enable
SBIT (ES0, SFR_IE, 4); // UART0 Interrupt Enable
SBIT (ET1, SFR_IE, 3); // Timer 1 Interrupt Enable
SBIT (EX1, SFR_IE, 2); // External Interrupt 1 Enable
SBIT (ET0, SFR_IE, 1); // Timer 0 Interrupt Enable
SBIT (EX0, SFR_IE, 0); // External Interrupt 0 Enable
// IP 0xB8
// Bit7 UNUSED
SBIT (PSPI0, SFR_IP, 6); // SPI0 Priority
SBIT (PT2, SFR_IP, 5); // Timer 2 Priority
SBIT (PS0, SFR_IP, 4); // UART0 Priority
SBIT (PT1, SFR_IP, 3); // Timer 1 Priority
SBIT (PX1, SFR_IP, 2); // External Interrupt 1 Priority
SBIT (PT0, SFR_IP, 1); // Timer 0 Priority
SBIT (PX0, SFR_IP, 0); // External Interrupt 0 Priority
// SMB0CN 0xC0
SBIT (MASTER, SFR_SMB0CN, 7); // SMBus0 Master/Slave
SBIT (TXMODE, SFR_SMB0CN, 6); // SMBus0 Transmit Mode
SBIT (STA, SFR_SMB0CN, 5); // SMBus0 Start Flag
SBIT (STO, SFR_SMB0CN, 4); // SMBus0 Stop Flag
SBIT (ACKRQ, SFR_SMB0CN, 3); // SMBus0 Acknowledge Request
SBIT (ARBLOST, SFR_SMB0CN, 2); // SMBus0 Arbitration Lost
SBIT (ACK, SFR_SMB0CN, 1); // SMBus0 Acknowledge Flag
SBIT (SI, SFR_SMB0CN, 0); // SMBus0 Interrupt Pending Flag
// TMR2CN 0xC8
SBIT (TF2H, SFR_TMR2CN, 7); // Timer 2 High Byte Overflow Flag
SBIT (TF2L, SFR_TMR2CN, 6); // Timer 2 Low Byte Overflow Flag
SBIT (TF2LEN, SFR_TMR2CN, 5); // Timer 2 Low Byte Interrupt Enable
SBIT (TF2CEN, SFR_TMR2CN, 4); // Timer 2 Lfo Capture Enable
SBIT (T2SPLIT, SFR_TMR2CN, 3); // Timer 2 Split Mode Enable
SBIT (TR2, SFR_TMR2CN, 2); // Timer 2 On/Off Control
// Bit6 UNUSED
SBIT (T2XCLK, SFR_TMR2CN, 0); // Timer 2 External Clock Select
// PSW 0xD0
SBIT (CY, SFR_PSW, 7); // Carry Flag
SBIT (AC, SFR_PSW, 6); // Auxiliary Carry Flag
SBIT (F0, SFR_PSW, 5); // User Flag 0
SBIT (RS1, SFR_PSW, 4); // Register Bank Select 1
SBIT (RS0, SFR_PSW, 3); // Register Bank Select 0
SBIT (OV, SFR_PSW, 2); // Overflow Flag
SBIT (F1, SFR_PSW, 1); // User Flag 1
SBIT (P, SFR_PSW, 0); // Accumulator Parity Flag
// PCA0CN 0xD8
SBIT (CF, SFR_PCA0CN, 7); // PCA0 Counter Overflow Flag
SBIT (CR, SFR_PCA0CN, 6); // PCA0 Counter Run Control Bit
SBIT (CCF5, SFR_PCA0CN, 5); // PCA0 Module 5 Interrupt Flag
SBIT (CCF4, SFR_PCA0CN, 4); // PCA0 Module 4 Interrupt Flag
SBIT (CCF3, SFR_PCA0CN, 3); // PCA0 Module 3 Interrupt Flag
SBIT (CCF2, SFR_PCA0CN, 2); // PCA0 Module 2 Interrupt Flag
SBIT (CCF1, SFR_PCA0CN, 1); // PCA0 Module 1 Interrupt Flag
SBIT (CCF0, SFR_PCA0CN, 0); // PCA0 Module 0 Interrupt Flag
// ADC0CN 0xE8
SBIT (AD0EN, SFR_ADC0CN, 7); // ADC0 Enable
SBIT (AD0TM, SFR_ADC0CN, 6); // ADC0 Track Mode
SBIT (AD0INT, SFR_ADC0CN, 5); // ADC0 EOC Interrupt Flag
SBIT (AD0BUSY, SFR_ADC0CN, 4); // ADC0 Busy Flag
SBIT (AD0WINT, SFR_ADC0CN, 3); // ADC0 Window Interrupt Flag
SBIT (AD0CM2, SFR_ADC0CN, 2); // ADC0 Convert Start Mode Bit 2
SBIT (AD0CM1, SFR_ADC0CN, 1); // ADC0 Convert Start Mode Bit 1
SBIT (AD0CM0, SFR_ADC0CN, 0); // ADC0 Convert Start Mode Bit 0
// SPI0CN 0xF8
SBIT (SPIF, SFR_SPI0CN, 7); // SPI0 Interrupt Flag
SBIT (WCOL, SFR_SPI0CN, 6); // SPI0 Write Collision Flag
SBIT (MODF, SFR_SPI0CN, 5); // SPI0 Mode Fault Flag
SBIT (RXOVRN, SFR_SPI0CN, 4); // SPI0 RX Overrun Flag
SBIT (NSSMD1, SFR_SPI0CN, 3); // SPI0 Slave Select Mode 1
SBIT (NSSMD0, SFR_SPI0CN, 2); // SPI0 Slave Select Mode 0
SBIT (TXBMT, SFR_SPI0CN, 1); // SPI0 TX Buffer Empty Flag
SBIT (SPIEN, SFR_SPI0CN, 0); // SPI0 SPI0 Enable
//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------
#define INTERRUPT_INT0 0 // External Interrupt 0
#define INTERRUPT_TIMER0 1 // Timer0 Overflow
#define INTERRUPT_INT1 2 // External Interrupt 1
#define INTERRUPT_TIMER1 3 // Timer1 Overflow
#define INTERRUPT_UART0 4 // Serial Port 0
#define INTERRUPT_TIMER2 5 // Timer2 Overflow
#define INTERRUPT_SPI0 6 // Serial Peripheral Interface 0
#define INTERRUPT_SMBUS0 7 // SMBus0 Interface
// Interrupt 8 is RESERVED
#define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison
#define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion
#define INTERRUPT_PCA0 11 // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0 12 // Comparator0
#define INTERRUPT_COMPARATOR1 13 // Comparator1
#define INTERRUPT_TIMER3 14 // Timer3 Overflow
// Interrupt 15 is RESERVED
#define INTERRUPT_PORT_MATCH 16 // Port Match
//-----------------------------------------------------------------------------
// SFR Page Definitions
//-----------------------------------------------------------------------------
#define CONFIG_PAGE 0x0F // SYSTEM AND PORT CONFIGURATION PAGE
#define LEGACY_PAGE 0x00 // LEGACY SFR PAGE
#define TIMER01_PAGE 0x00 // TIMER 0 AND TIMER 1
#define CPT0_PAGE 0x00 // COMPARATOR 0
#define CPT1_PAGE 0x00 // COMPARATOR 1
#define UART0_PAGE 0x00 // UART 0
#define SPI0_PAGE 0x00 // SPI 0
#define EMI0_PAGE 0x0F // EXTERNAL MEMORY INTERFACE
#define ADC0_PAGE 0x00 // ADC 0
#define SMB0_PAGE 0x00 // SMBUS 0
#define TMR2_PAGE 0x00 // TIMER 2
#define TMR3_PAGE 0x00 // TIMER 3
#define DAC0_PAGE 0x00 // DAC 0
#define PCA0_PAGE 0x00 // PCA 0
#define PLL0_PAGE 0x0F // PLL 0
#define MAC0_PAGE 0x00 // MAC 0
#define MATCH_PAGE 0x00 // PORT0, PORT1, PORT2 MATCH
//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------
#endif // #define C8051F360_DEFS_H
//-----------------------------------------------------------------------------
// End Of File
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