c8051f020_defs.h

芯科原厂所有c8051fxx程序的例子。

//-----------------------------------------------------------------------------
// C8051F020_defs.h
//-----------------------------------------------------------------------------
// Copyright 2007, Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Register/bit definitions for the C8051F02x family.
// **Important Note**: The compiler_defs.h header file should be included 
// before including this header file.
//
// Target:         C8051F020, 'F021, 'F022, 'F023
// Tool chain:     Generic
// Command Line:   None
//
// Release 1.3 - 07 AUG 2007 (PKC)
//    -Removed #include <compiler_defs.h>. The C source file should include it.
// Release 1.2 - 09 JUL 2007 (PKC)
//    -Reformatted header file to enable portable SFR definitions

//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------

#ifndef C8051F020_DEFS_H
#define C8051F020_DEFS_H

//-----------------------------------------------------------------------------
// Byte Registers
//-----------------------------------------------------------------------------

SFR (P0, 0x80);                        // Port 0 Latch
SFR (SP, 0x81);                        // Stack Pointer
SFR (DPL, 0x82);                       // Data Pointer Low
SFR (DPH, 0x83);                       // Data Pointer High
SFR (P4, 0x84);                        // Port 4 Latch
SFR (P5, 0x85);                        // Port 5 Latch
SFR (P6, 0x86);                        // Port 6 Latch
SFR (PCON, 0x87);                      // Power Control
SFR (TCON, 0x88);                      // Timer/Counter Control
SFR (TMOD, 0x89);                      // Timer/Counter Mode
SFR (TL0, 0x8A);                       // Timer/Counter 0 Low
SFR (TL1, 0x8B);                       // Timer/Counter 1 Low
SFR (TH0, 0x8C);                       // Timer/Counter 0 High
SFR (TH1, 0x8D);                       // Timer/Counter 1 High
SFR (CKCON, 0x8E);                     // Clock Control
SFR (PSCTL, 0x8F);                     // Program Store R/W Control
SFR (P1, 0x90);                        // Port 1 Latch
SFR (TMR3CN, 0x91);                    // Timer/Counter 3 Control
SFR (TMR3RLL, 0x92);                   // Timer/Counter 3 Reload Low
SFR (TMR3RLH, 0x93);                   // Timer/Counter 3 Reload High
SFR (TMR3L, 0x94);                     // Timer/Counter 3 Low
SFR (TMR3H, 0x95);                     // Timer/Counter 3 High
SFR (P7, 0x96);                        // Port 7 Latch
SFR (SCON0, 0x98);                     // Serial Port UART0 Control
SFR (SBUF0, 0x99);                     // Serial Port UART0 Data Buffer
SFR (SPI0CFG, 0x9A);                   // SPI0 Configuration
SFR (SPI0DAT, 0x9B);                   // SPI0 Data
SFR (ADC1, 0x9C);                      // ADC1 Data
SFR (SPI0CKR, 0x9D);                   // SPI0 Clock Rate Control
SFR (CPT0CN, 0x9E);                    // Comparator 0 Control
SFR (CPT1CN, 0x9F);                    // Comparator 1 Control
SFR (P2, 0xA0);                        // Port 2 Latch
SFR (EMI0TC, 0xA1);                    // EMIF Timing Control
SFR (EMI0CF, 0xA3);                    // EMIF Configuration
SFR (P0MDOUT, 0xA4);                   // Port 0 Output Mode Configuration
SFR (P1MDOUT, 0xA5);                   // Port 1 Output Mode Configuration
SFR (P2MDOUT, 0xA6);                   // Port 2 Output Mode Configuration
SFR (P3MDOUT, 0xA7);                   // Port 3 Output Mode Configuration
SFR (IE, 0xA8);                        // Interrupt Enable
SFR (SADDR0, 0xA9);                    // Serial Port UART0 Slave Address
SFR (ADC1CN, 0xAA);                    // ADC1 Control
SFR (ADC1CF, 0xAB);                    // ADC1 Analog Mux Configuration
SFR (AMX1SL, 0xAC);                    // ADC1 Analog Mux Channel Select
SFR (P3IF, 0xAD);                      // Port 3 External Interrupt Flags
SFR (SADEN1, 0xAE);                    // Serial Port UART1 Slave Address Mask
SFR (EMI0CN, 0xAF);                    // EMIF Control
SFR (P3, 0xB0);                        // Port 3 Latch
SFR (OSCXCN, 0xB1);                    // External Oscillator Control
SFR (OSCICN, 0xB2);                    // Internal Oscillator Control
SFR (P74OUT, 0xB5);                    // Ports 4 - 7 Output Mode
SFR (FLSCL, 0xB6);                     // Flash Memory Timing Prescaler
SFR (FLACL, 0xB7);                     // Flash Acess Limit
SFR (IP, 0xB8);                        // Interrupt Priority
SFR (SADEN0, 0xB9);                    // Serial Port UART0 Slave Address Mask
SFR (AMX0CF, 0xBA);                    // ADC0 Mux Configuration
SFR (AMX0SL, 0xBB);                    // ADC0 Mux Channel Selection
SFR (ADC0CF, 0xBC);                    // ADC0 Configuration
SFR (P1MDIN, 0xBD);                    // Port 1 Input Mode
SFR (ADC0L, 0xBE);                     // ADC0 Data Low
SFR (ADC0H, 0xBF);                     // ADC0 Data High
SFR (SMB0CN, 0xC0);                    // SMBus0 Control
SFR (SMB0STA, 0xC1);                   // SMBus0 Status
SFR (SMB0DAT, 0xC2);                   // SMBus0 Data
SFR (SMB0ADR, 0xC3);                   // SMBus0 Slave Address
SFR (ADC0GTL, 0xC4);                   // ADC0 Greater-Than Register Low
SFR (ADC0GTH, 0xC5);                   // ADC0 Greater-Than Register High
SFR (ADC0LTL, 0xC6);                   // ADC0 Less-Than Register Low
SFR (ADC0LTH, 0xC7);                   // ADC0 Less-Than Register High
SFR (T2CON, 0xC8);                     // Timer/Counter 2 Control
SFR (T4CON, 0xC9);                     // Timer/Counter 4 Control
SFR (RCAP2L, 0xCA);                    // Timer/Counter 2 Capture Low
SFR (RCAP2H, 0xCB);                    // Timer/Counter 2 Capture High
SFR (TL2, 0xCC);                       // Timer/Counter 2 Low
SFR (TH2, 0xCD);                       // Timer/Counter 2 High
SFR (SMB0CR, 0xCF);                    // SMBus0 Clock Rate
SFR (PSW, 0xD0);                       // Program Status Word
SFR (REF0CN, 0xD1);                    // Voltage Reference 0 Control
SFR (DAC0L, 0xD2);                     // DAC0 Register Low
SFR (DAC0H, 0xD3);                     // DAC0 Register High
SFR (DAC0CN, 0xD4);                    // DAC0 Control
SFR (DAC1L, 0xD5);                     // DAC1 Register Low
SFR (DAC1H, 0xD6);                     // DAC1 Register High
SFR (DAC1CN, 0xD7);                    // DAC1 Control
SFR (PCA0CN, 0xD8);                    // PCA0 Control
SFR (PCA0MD, 0xD9);                    // PCA0 Mode
SFR (PCA0CPM0, 0xDA);                  // PCA0 Module 0 Mode Register
SFR (PCA0CPM1, 0xDB);                  // PCA0 Module 1 Mode Register
SFR (PCA0CPM2, 0xDC);                  // PCA0 Module 2 Mode Register
SFR (PCA0CPM3, 0xDD);                  // PCA0 Module 3 Mode Register
SFR (PCA0CPM4, 0xDE);                  // PCA0 Module 4 Mode Register
SFR (ACC, 0xE0);                       // Accumulator
SFR (XBR0, 0xE1);                      // Port I/O Crossbar Control 0
SFR (XBR1, 0xE2);                      // Port I/O Crossbar Control 1
SFR (XBR2, 0xE3);                      // Port I/O Crossbar Control 2
SFR (RCAP4L, 0xE4);                    // Timer 4 Capture Register Low
SFR (RCAP4H, 0xE5);                    // Timer 4 Capture Register High
SFR (EIE1, 0xE6);                      // External Interrupt Enable 1
SFR (EIE2, 0xE7);                      // External Interrupt Enable 2
SFR (ADC0CN, 0xE8);                    // ADC0 Control
SFR (PCA0L, 0xE9);                     // PCA0 Counter Low
SFR (PCA0CPL0, 0xEA);                  // PCA0 Capture 0 Low
SFR (PCA0CPL1, 0xEB);                  // PCA0 Capture 1 Low
SFR (PCA0CPL2, 0xEC);                  // PCA0 Capture 2 Low
SFR (PCA0CPL3, 0xED);                  // PCA0 Capture 3 Low
SFR (PCA0CPL4, 0xEE);                  // PCA0 Capture 4 Low
SFR (RSTSRC, 0xEF);                    // Reset Source Configuration/Status
SFR (B, 0xF0);                         // B Register
SFR (SCON1, 0xF1);                     // Serial Port UART1 Control
SFR (SBUF1, 0xF2);                     // Serail Port UART1 Data
SFR (SADDR1, 0xF3);                    // Serail Port UART1 Slave Address
SFR (TL4, 0xF4);                       // Timer/Counter 4 Low
SFR (TH4, 0xF5);                       // Timer/Counter 4 High
SFR (EIP1, 0xF6);                      // External Interrupt Priority 1
SFR (EIP2, 0xF7);                      // External Interrupt Priority 2
SFR (SPI0CN, 0xF8);                    // SPI0 Control
SFR (PCA0H, 0xF9);                     // PCA0 Counter High
SFR (PCA0CPH0, 0xFA);                  // PCA0 Capture 0 High
SFR (PCA0CPH1, 0xFB);                  // PCA0 Capture 1 High
SFR (PCA0CPH2, 0xFC);                  // PCA0 Capture 2 High
SFR (PCA0CPH3, 0xFD);                  // PCA0 Capture 3 High
SFR (PCA0CPH4, 0xFE);                  // PCA0 Capture 4 High
SFR (WDTCN, 0xFF);                     // Watchdog Timer Control

//-----------------------------------------------------------------------------
// 16-bit Register Definitions (might not be supported by all compilers)
//-----------------------------------------------------------------------------

SFR16 (DP, 0x82);                      // Data Pointer
SFR16 (TMR3RL, 0x92);                  // Timer3 Reload Value
SFR16 (TMR3, 0x94);                    // Timer3 Counter
SFR16 (ADC0, 0xBE);                    // ADC0 Data
SFR16 (ADC0GT, 0xC4);                  // ADC0 Greater Than Window
SFR16 (ADC0LT, 0xC6);                  // ADC0 Less Than Window
SFR16 (RCAP2, 0xCA);                   // Timer2 Capture/Reload
SFR16 (T2, 0xCC);                      // Timer2 Counter
SFR16 (TMR2RL, 0xCA);                  // Timer2 Capture/Reload
SFR16 (TMR2, 0xCC);                    // Timer2 Counter