c8051f020_defs.h

芯科原厂所有c8051fxx程序的例子。

SFR16 (RCAP4, 0xE4);                   // Timer4 Capture/Reload
SFR16 (T4, 0xF4);                      // Timer4 Counter
SFR16 (TMR4RL, 0xE4);                  // Timer4 Capture/Reload
SFR16 (TMR4, 0xF4);                    // Timer4 Counter
SFR16 (DAC0, 0xD2);                    // DAC0 Data
SFR16 (DAC1, 0xD5);                    // DAC1 Data

//-----------------------------------------------------------------------------
// Address Definitions for bit-addressable SFRs
//-----------------------------------------------------------------------------

#define SFR_P0       0x80
#define SFR_TCON     0x88
#define SFR_P1       0x90
#define SFR_SCON0    0x98
#define SFR_P2       0xA0
#define SFR_IE       0xA8
#define SFR_P3       0xB0
#define SFR_IP       0xB8
#define SFR_SMB0CN   0xC0
#define SFR_T2CON    0xC8
#define SFR_PSW      0xD0
#define SFR_PCA0CN   0xD8
#define SFR_ACC      0xE0
#define SFR_ADC0CN   0xE8
#define SFR_B        0xF0
#define SFR_SPI0CN   0xF8

//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------

// TCON 0x88
SBIT (TF1, SFR_TCON, 7);               // Timer 1 Overflow Flag
SBIT (TR1, SFR_TCON, 6);               // Timer 1 On/Off Control
SBIT (TF0, SFR_TCON, 5);               // Timer 0 Overflow Flag
SBIT (TR0, SFR_TCON, 4);               // Timer 0 On/Off Control
SBIT (IE1, SFR_TCON, 3);               // Ext. Interrupt 1 Edge Flag
SBIT (IT1, SFR_TCON, 2);               // Ext. Interrupt 1 Type
SBIT (IE0, SFR_TCON, 1);               // Ext. Interrupt 0 Edge Flag
SBIT (IT0, SFR_TCON, 0);               // Ext. Interrupt 0 Type

// SCON0 0x98
SBIT (SM00, SFR_SCON0, 7);             // Serial Mode Control Bit 0
SBIT (SM10, SFR_SCON0, 6);             // Serial Mode Control Bit 1
SBIT (SM20, SFR_SCON0, 5);             // Multiprocessor Communication Enable
SBIT (REN0, SFR_SCON0, 4);             // Receive Enable
SBIT (TB80, SFR_SCON0, 3);             // Transmit Bit 8
SBIT (RB80, SFR_SCON0, 2);             // Receive Bit 8
SBIT (TI0, SFR_SCON0, 1);              // Transmit Interrupt Flag
SBIT (RI0, SFR_SCON0, 0);              // Receive Interrupt Flag

// IE 0xA8
SBIT (EA, SFR_IE, 7);                  // Global Interrupt Enable
SBIT (IEGF0, SFR_IE, 6);               // General Purpose Flag 0
SBIT (ET2, SFR_IE, 5);                 // Timer 2 Interrupt Enable
SBIT (ES0, SFR_IE, 4);                 // Uart0 Interrupt Enable
SBIT (ET1, SFR_IE, 3);                 // Timer 1 Interrupt Enable
SBIT (EX1, SFR_IE, 2);                 // External Interrupt 1 Enable
SBIT (ET0, SFR_IE, 1);                 // Timer 0 Interrupt Enable
SBIT (EX0, SFR_IE, 0);                 // External Interrupt 0 Enable

// IP 0xB8
                                       // Bit7 UNUSED
                                       // Bit6 UNUSED
SBIT (PT2, SFR_IP, 5);                 // Timer 2 Priority
SBIT (PS, SFR_IP, 4);                  // Serial Port Priority
SBIT (PT1, SFR_IP, 3);                 // Timer 1 Priority
SBIT (PX1, SFR_IP, 2);                 // External Interrupt 1 Priority
SBIT (PT0, SFR_IP, 1);                 // Timer 0 Priority
SBIT (PX0, SFR_IP, 0);                 // External Interrupt 0 Priority

// SMB0CN 0xC0
SBIT (BUSY, SFR_SMB0CN, 7);            // SMBus 0 Busy
SBIT (ENSMB, SFR_SMB0CN, 6);           // SMBus 0 Enable
SBIT (STA, SFR_SMB0CN, 5);             // SMBus 0 Start Flag
SBIT (STO, SFR_SMB0CN, 4);             // SMBus 0 Stop Flag
SBIT (SI, SFR_SMB0CN, 3);              // SMBus 0 Interrupt Pending Flag
SBIT (AA, SFR_SMB0CN, 2);              // SMBus 0 Assert/Acknowledge Flag
SBIT (SMBFTE, SFR_SMB0CN, 1);          // SMBus 0 Free Timer Enable
SBIT (SMBTOE, SFR_SMB0CN, 0);          // SMBus 0 Timeout Enable

// T2CON 0xC8
SBIT (TF2, SFR_T2CON, 7);              // Timer 2 Overflow Flag
SBIT (EXF2, SFR_T2CON, 6);             // External Flag
SBIT (RCLK0, SFR_T2CON, 5);            // Uart0 Rx Clock Source
SBIT (TCLK0, SFR_T2CON, 4);            // Uart0 Tx Clock Source
SBIT (EXEN2, SFR_T2CON, 3);            // Timer 2 External Enable Flag
SBIT (TR2, SFR_T2CON, 2);              // Timer 2 On/Off Control
SBIT (CT2, SFR_T2CON, 1);              // Timer Or Counter Select
SBIT (CPRL2, SFR_T2CON, 0);            // Capture Or Reload Select

//  PSW 0xD0
SBIT (CY, SFR_PSW, 7);                 // Carry Flag
SBIT (AC, SFR_PSW, 6);                 // Auxiliary Carry Flag
SBIT (F0, SFR_PSW, 5);                 // User Flag 0
SBIT (RS1, SFR_PSW, 4);                // Register Bank Select 1
SBIT (RS0, SFR_PSW, 3);                // Register Bank Select 0
SBIT (OV, SFR_PSW, 2);                 // Overflow Flag
SBIT (F1, SFR_PSW, 1);                 // User Flag 1
SBIT (P, SFR_PSW, 0);                  // Accumulator Parity Flag

// PCA0CN 0xD8
SBIT (CF, SFR_PCA0CN, 7);              // PCA 0 Counter Overflow Flag
SBIT (CR, SFR_PCA0CN, 6);              // PCA 0 Counter Run Control Bit
                                       // Bit5 UNUSED
SBIT (CCF4, SFR_PCA0CN, 4);            // PCA 0 Module 4 Interrupt Flag
SBIT (CCF3, SFR_PCA0CN, 3);            // PCA 0 Module 3 Interrupt Flag
SBIT (CCF2, SFR_PCA0CN, 2);            // PCA 0 Module 2 Interrupt Flag
SBIT (CCF1, SFR_PCA0CN, 1);            // PCA 0 Module 1 Interrupt Flag
SBIT (CCF0, SFR_PCA0CN, 0);            // PCA 0 Module 0 Interrupt Flag

// ADC0CN 0xE8
SBIT (AD0EN, SFR_ADC0CN, 7);           // ADC 0 Enable
SBIT (AD0TM, SFR_ADC0CN, 6);           // ADC 0 Track Mode
SBIT (AD0INT, SFR_ADC0CN, 5);          // ADC 0 Converision Complete Interrupt Flag
SBIT (AD0BUSY, SFR_ADC0CN, 4);         // ADC 0 Busy Flag
SBIT (AD0CM1, SFR_ADC0CN, 3);          // ADC 0 Start Of Conversion Mode Bit 1
SBIT (AD0CM0, SFR_ADC0CN, 2);          // ADC 0 Start Of Conversion Mode Bit 0
SBIT (AD0WINT, SFR_ADC0CN, 1);         // ADC 0 Window Compare Interrupt Flag
SBIT (AD0LJST, SFR_ADC0CN, 0);         // ADC 0 Right Justify Data Bit

// SPI0CN 0xF8
SBIT (SPIF, SFR_SPI0CN, 7);            // SPI 0 Interrupt Flag
SBIT (WCOL, SFR_SPI0CN, 6);            // SPI 0 Write Collision Flag
SBIT (MODF, SFR_SPI0CN, 5);            // SPI 0 Mode Fault Flag
SBIT (RXOVRN, SFR_SPI0CN, 4);          // SPI 0 Rx Overrun Flag
SBIT (TXBSY, SFR_SPI0CN, 3);           // SPI 0 Tx Busy Flag
SBIT (SLVSEL, SFR_SPI0CN, 2);          // SPI 0 Slave Select
SBIT (MSTEN, SFR_SPI0CN, 1);           // SPI 0 Master Enable
SBIT (SPIEN, SFR_SPI0CN, 0);           // SPI 0 SPI Enable

//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------

#define INTERRUPT_INT0           0     // External Interrupt 0
#define INTERRUPT_TIMER0         1     // Timer0 Overflow
#define INTERRUPT_INT1           2     // External Interrupt 1
#define INTERRUPT_TIMER1         3     // Timer1 Overflow
#define INTERRUPT_UART0          4     // Serial Port UART0
#define INTERRUPT_TIMER2         5     // Timer2 Overflow
#define INTERRUPT_SPI0           6     // SPI0 Interface
#define INTERRUPT_SMBUS0         7     // SMBus0 Interface
#define INTERRUPT_ADC0_WINDOW    8     // ADC0 Window Comparison
#define INTERRUPT_PCA0           9     // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0F   10    // Comparator0 Falling Edge
#define INTERRUPT_COMPARATOR0R   11    // Comparator0 Rising Edge
#define INTERRUPT_COMPARATOR1F   12    // Comparator1 Falling Edge
#define INTERRUPT_COMPARATOR1R   13    // Comparator1 Rising Edge
#define INTERRUPT_TIMER3         14    // Timer3 Overflow
#define INTERRUPT_ADC0_EOC       15    // ADC0 End Of Conversion
#define INTERRUPT_TIMER4         16    // Timer4 Overflow
#define INTERRUPT_ADC1_EOC       17    // ADC1 End Of Conversion
#define INTERRUPT_INT6           18    // External Interrupt 6
#define INTERRUPT_INT7           19    // External Interrupt 7
#define INTERRUPT_UART1          20    // Serial Port UART1
#define INTERRUPT_XTAL_READY     21    // External Crystal Oscillator Ready

//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------

#endif                                 // #define C8051F020_DEFS_H

//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------