c8051f520a_defs.h

来自「芯科原厂所有c8051fxx程序的例子。」· C头文件 代码 · 共 311 行 · 第 1/2 页

//-----------------------------------------------------------------------------
// C8051F520A_defs.h
//-----------------------------------------------------------------------------
// Copyright 2006 Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Register/bit definitions for the C8051F52xA/'F53xA family.
//
// Target:         C8051F52xA, 'F53xA
// Tool chain:     Keil, SDCC
// Command Line:   None
//
// Release 1.3
//    -All changes by TP
//    -25 JUN 2008
//    Added LIN indirect registers
//
// Release 1.2
//    -All changes by TP
//    -29 JAN 2008
//    Updated to use "compiler_defs.h"
//
// Release 1.1
//    -All changes by CG
//    -07 AUG 2007
//    Changed the name of the register AMX0SL to ADC0MX. (0xBB address)
//
// Release 1.0
//    -All changes by CG/PKC
//    -04 OCT 2006
//    Initial Release
//

//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------

#ifndef C8051F520A_H
#define C8051F520A_H

#include <compiler_defs.h>

//-----------------------------------------------------------------------------
// Byte Registers
//-----------------------------------------------------------------------------


SFR (P0, 0x80);                        // Port 0 Latch
SFR (SP, 0x81);                        // Stack Pointer
SFR (DPL, 0x82);                       // Data Pointer - Low byte
SFR (DPH, 0x83);                       // Data Pointer - High byte
SFR (PCON, 0x87);                      // Power Control
SFR (TCON, 0x88);                      // Timer Control
SFR (TMOD, 0x89);                      // Timer Mode
SFR (TL0, 0x8A);                       // Timer 0 - Low byte
SFR (TL1, 0x8B);                       // Timer 1 - Low byte
SFR (TH0, 0x8C);                       // Timer 0 - High byte
SFR (TH1, 0x8D);                       // Timer 1 - High byte
SFR (CKCON, 0x8E);                     // Clock Control
SFR (PSCTL, 0x8F);                     // Program Store R/W Control
SFR (P1, 0x90);                        // Port 1 Latch
SFR (LINADDR, 0x92);                   // LIN Indirect Access Address
SFR (LINDATA, 0x93);                   // LIN Indirect Access Data
SFR (LINCF, 0x95);                     // LIN Configuration
SFR (SCON0, 0x98);                     // UART0 Control
SFR (SBUF0, 0x99);                     // UART0 Buffer
SFR (CPT0CN, 0x9B);                    // Comparator 0 Control
SFR (CPT0MD, 0x9D);                    // Comparator 0 Mode
SFR (CPT0MX, 0x9F);                    // Comparator 0 Mux
SFR (SPI0CFG, 0xA1);                   // SPI0 Configuration
SFR (SPI0CKR, 0xA2);                   // SPI0 Clock Rate
SFR (SPI0DAT, 0xA3);                   // SPI0 Data
SFR (P0MDOUT, 0xA4);                   // Port 0 Output Mode Configuration
SFR (P1MDOUT, 0xA5);                   // Port 1 Output Mode Configuration
SFR (IE, 0xA8);                        // Interrupt Enable
SFR (CLKSEL, 0xA9);                    // Clock Select
SFR (OSCIFIN, 0xB0);                   // Internal Fine Oscillator Calibration
SFR (OSCXCN, 0xB1);                    // External Oscillator Control
SFR (OSCICN, 0xB2);                    // Internal Oscillator Control
SFR (OSCICL, 0xB3);                    // Internal Oscillator Calibration
SFR (FLKEY, 0xB7);                     // Flash Lock & Key
SFR (IP, 0xB8);                        // Interrupt Priority
SFR (ADC0TK, 0xBA);                    // ADC0 Tracking
SFR (ADC0MX, 0xBB);                    // ADC0 Mux Channel Selection
SFR (ADC0CF, 0xBC);                    // ADC0 CONFIGURATION
SFR (ADC0L, 0xBD);                     // ADC0 LSB Result
SFR (ADC0H, 0xBE);                     // ADC0 Data
SFR (P1MASK, 0xBF);                    // Port 1 Mask
SFR (ADC0GTL, 0xC3);                   // ADC0 Greater-Than Compare Low
SFR (ADC0GTH, 0xC4);                   // ADC0 Greater-Than Compare High
SFR (ADC0LTL, 0xC5);                   // ADC0 Less-Than Compare Word Low
SFR (ADC0LTH, 0xC6);                   // ADC0 Less-Than Compare Word High
SFR (P0MASK, 0xC7);                    // Port 1 Mask
SFR (TMR2CN, 0xC8);                    // Timer 2 Control
SFR (REG0CN, 0xC9);                    // Regulator Control
SFR (TMR2RLL, 0xCA);                   // Timer 2 Reload Low
SFR (TMR2RLH, 0xCB);                   // Timer 2 Reload High
SFR (TMR2L, 0xCC);                     // Timer 2 Low Byte
SFR (TMR2H, 0xCD);                     // Timer 2 High Byte
SFR (P1MAT, 0xCF);                     // Port1 Match
SFR (PSW, 0xD0);                       // Program Status Word
SFR (REF0CN, 0xD1);                    // Voltage Reference 0 Control
SFR (P0SKIP, 0xD4);                    // Port 0 Skip
SFR (P1SKIP, 0xD5);                    // Port 1 Skip
SFR (P0MAT, 0xD7);                     // Port 0 Match
SFR (PCA0CN, 0xD8);                    // PCA0 Control
SFR (PCA0MD, 0xD9);                    // PCA0 Mode
SFR (PCA0CPM0, 0xDA);                  // PCA0 Module 0 Mode
SFR (PCA0CPM1, 0xDB);                  // PCA0 Module 1 Mode
SFR (PCA0CPM2, 0xDC);                  // PCA0 Module 2 Mode
SFR (ACC, 0xE0);                       // Accumulator
SFR (XBR0, 0xE1);                      // Digital Crossbar Configuration 0
SFR (XBR1, 0xE2);                      // Digital Crossbar Configuration 1
SFR (IT01CF, 0xE4);                    // INT0/INT1 Configuration
SFR (EIE1, 0xE6);                      // Extended Interrupt Enable 1
SFR (ADC0CN, 0xE8);                    // ADC 0 Control
SFR (PCA0CPL1, 0xE9);                  // PCA0 Module 1 Capture/Compare Low Byte
SFR (PCA0CPH1, 0xEA);                  // PCA0 Module 1 Capture/Compare High Byte
SFR (PCA0CPL2, 0xEB);                  // PCA0 Module 2 Capture/Compare Low Byte
SFR (PCA0CPH2, 0xEC);                  // PCA0 Module 2 Capture/Compare High Byte
SFR (RSTSRC, 0xEF);                    // Reset Source Configuration/Status
SFR (B, 0xF0);                         // B Register
SFR (P0MDIN, 0xF1);                    // Port 0 Input Mode
SFR (P1MDIN, 0xF2);                    // Port 1 Input Mode
SFR (EIP1, 0xF6);                      // Extended Interrupt Priority 1
SFR (SPI0CN, 0xF8);                    // SPI0 Control
SFR (PCA0L, 0xF9);                     // PCA0 Counter Low Byte
SFR (PCA0H, 0xFA);                     // PCA0 Counter High Byte
SFR (PCA0CPL0, 0xFB);                  // PCA Module 0 Capture/Compare Low Byte
SFR (PCA0CPH0, 0xFC);                  // PCA Module 0 Capture/Compare High Byte
SFR (VDDMON, 0xFF);                    // VDD Monitor

//-----------------------------------------------------------------------------
// 16-bit Register Definitions (might not be supported by all compilers)
//-----------------------------------------------------------------------------

SFR16 (DP, 0x82);                      // Data Pointer
SFR16 (ADC0, 0xBD);                    // ADC0 Data
SFR16 (ADC0GT, 0xC3);                  // ADC0 Greater-Than Compare
SFR16 (ADC0LT, 0xC5);                  // ADC0 Less-Than Compare
SFR16 (TMR2RL, 0xCA);                  // Timer 2 Reload
SFR16 (TMR2, 0xCC);                    // Timer 2 Counter
SFR16 (PCA0, 0xF9);                    // PCA0 Counter
SFR16 (PCA0CP0, 0xFB);                 // PCA0 Module 0 Capture/Compare
SFR16 (PCA0CP1, 0xE9);                 // PCA0 Module 1 Capture/Compare
SFR16 (PCA0CP2, 0xEB);                 // PCA0 Module 2 Capture/Compare

//-----------------------------------------------------------------------------
// LIN0 Indirect Registers
//-----------------------------------------------------------------------------

#define  LIN0DT1   0x00                // LIN0 Data Byte 1
#define  LIN0DT2   0x01                // LIN0 Data Byte 2
#define  LIN0DT3   0x02                // LIN0 Data Byte 3