📄 2440addr.h
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// SPI
#define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
#define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
#define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
#define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler
#define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
#define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
#define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
#define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
#define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
#define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler
#define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
#define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
// SD Interface
#define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control
#define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler
#define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
#define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
#define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
#define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0
#define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1
#define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2
#define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3
#define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
#define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
#define rSDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control
#define rSDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter
#define rSDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status
#define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
#define rSDIIMSK (*(volatile unsigned *)0x5a00003c) //SDI interrupt mask. edited for 2440A
#ifdef __BIG_ENDIAN /* edited for 2440A */
#define rSDIDAT (*(volatile unsigned *)0x5a00004c) //SDI data
#define SDIDAT 0x5a00004c
#else // Little Endian
#define rSDIDAT (*(volatile unsigned *)0x5a000040) //SDI data
#define SDIDAT 0x5a000040
#endif //SD Interface
// Exception vector
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
// Interrupt vector
#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
#define pISR_CAM (*(unsigned *)(_ISR_STARTADDRESS+0x38)) // Added for 2440.
#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
#define pISR_WDT_AC97 (*(unsigned *)(_ISR_STARTADDRESS+0x44)) //Changed to pISR_WDT_AC97 for 2440A
#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
#define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x60))
#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
#define pISR_NFCON (*(unsigned *)(_ISR_STARTADDRESS+0x80)) // Added for 2440.
#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))
// PENDING BIT
#define BIT_EINT0 (0x1)
#define BIT_EINT1 (0x1<<1)
#define BIT_EINT2 (0x1<<2)
#define BIT_EINT3 (0x1<<3)
#define BIT_EINT4_7 (0x1<<4)
#define BIT_EINT8_23 (0x1<<5)
#define BIT_CAM (0x1<<6) // Added for 2440.
#define BIT_BAT_FLT (0x1<<7)
#define BIT_TICK (0x1<<8)
#define BIT_WDT_AC97 (0x1<<9) // Changed from BIT_WDT to BIT_WDT_AC97 for 2440A
#define BIT_TIMER0 (0x1<<10)
#define BIT_TIMER1 (0x1<<11)
#define BIT_TIMER2 (0x1<<12)
#define BIT_TIMER3 (0x1<<13)
#define BIT_TIMER4 (0x1<<14)
#define BIT_UART2 (0x1<<15)
#define BIT_LCD (0x1<<16)
#define BIT_DMA0 (0x1<<17)
#define BIT_DMA1 (0x1<<18)
#define BIT_DMA2 (0x1<<19)
#define BIT_DMA3 (0x1<<20)
#define BIT_SDI (0x1<<21)
#define BIT_SPI0 (0x1<<22)
#define BIT_UART1 (0x1<<23)
#define BIT_NFCON (0x1<<24) // Added for 2440.
#define BIT_USBD (0x1<<25)
#define BIT_USBH (0x1<<26)
#define BIT_IIC (0x1<<27)
#define BIT_UART0 (0x1<<28)
#define BIT_SPI1 (0x1<<29)
#define BIT_RTC (0x1<<30)
#define BIT_ADC (0x1<<31)
#define BIT_ALLMSK (0xffffffff)
#define BIT_SUB_ALLMSK (0x7fff) //Changed from 0x7ff to 0x7fff for 2440A
#define BIT_SUB_AC97 (0x1<<14) //Added for 2440A
#define BIT_SUB_WDT (0x1<<13) //Added for 2440A
#define BIT_SUB_CAM_P (0x1<<12) // edited for 2440A.
#define BIT_SUB_CAM_C (0x1<<11) // edited for 2440A
#define BIT_SUB_ADC (0x1<<10)
#define BIT_SUB_TC (0x1<<9)
#define BIT_SUB_ERR2 (0x1<<8)
#define BIT_SUB_TXD2 (0x1<<7)
#define BIT_SUB_RXD2 (0x1<<6)
#define BIT_SUB_ERR1 (0x1<<5)
#define BIT_SUB_TXD1 (0x1<<4)
#define BIT_SUB_RXD1 (0x1<<3)
#define BIT_SUB_ERR0 (0x1<<2)
#define BIT_SUB_TXD0 (0x1<<1)
#define BIT_SUB_RXD0 (0x1<<0)
#define ClearPending(bit) {\
rSRCPND = bit;\
rINTPND = bit;\
rINTPND;\
}
//Wait until rINTPND is changed for the case that the ISR is very short.
////////////////////////////////////////////
// USB DEVICE DEFINITION START //
////////////////////////////////////////////
/* Power Management Register */
#define DISABLE_SUSPEND 0x00
#define ENABLE_SUSPEND 0x01
#define SUSPEND_MODE 0x02
#define MCU_RESUME 0x04
#define ISO_UPDATE 1<<7)
/* MAXP Register */
#define FIFO_SIZE_0 0x00 /* 0x00 * 8 = 0 */
#define FIFO_SIZE_8 0x01 /* 0x01 * 8 = 8 */
#define FIFO_SIZE_16 0x02 /* 0x02 * 8 = 16 */
#define FIFO_SIZE_32 0x04 /* 0x04 * 8 = 32 */
#define FIFO_SIZE_64 0x08 /* 0x08 * 8 = 64 */
/* ENDPOINT0 CSR (Control Status Register) : Mapped to IN CSR1 */
#define EP0_OUT_PKT_READY 0x01 /* USB sets, MCU clears by setting SERVICED_OUT_PKT_RDY */
#define EP0_IN_PKT_READY 0x02 /* MCU sets, USB clears after sending FIFO */
#define EP0_SENT_STALL 0x04 /* USB sets */
#define EP0_DATA_END 0x08 /* MCU sets */
#define EP0_SETUP_END 0x10 /* USB sets, MCU clears by setting SERVICED_SETUP_END */
#define EP0_SEND_STALL 0x20 /* MCU sets */
#define EP0_SERVICED_OUT_PKT_RDY 0x40 /* MCU writes 1 to clear OUT_PKT_READY */
#define EP0_SERVICED_SETUP_END 0x80 /* MCU writes 1 to clear SETUP_END */
#define EP0_WR_BITS 0xc0
//EP_INT_REG / EP_INT_EN_REG
#define EP0_INT 0x01 // Endpoint 0, Control
#define EP1_INT 0x02 // Endpoint 1, (Bulk-In)
#define EP2_INT 0x04 // Endpoint 2
#define EP3_INT 0x08 // Endpoint 3, (Bulk-Out)
#define EP4_INT 0x10 // Endpoint 4
//USB_INT_REG / USB_INT_EN_REG
#define SUSPEND_INT 0x01
#define RESUME_INT 0x02
#define RESET_INT 0x04
//IN_CSR1
#define EPI_IN_PKT_READY 0x01
#define EPI_UNDER_RUN 0x04
#define EPI_FIFO_FLUSH 0x08
#define EPI_SEND_STALL 0x10
#define EPI_SENT_STALL 0x20
#define EPI_CDT 0x40
#define EPI_WR_BITS (EPI_FIFO_FLUSH|EPI_IN_PKT_READY|EPI_CDT)
//(EPI_FIFO_FLUSH) is preferred (???)
//IN_CSR2
#define EPI_IN_DMA_INT_MASK (1<<4)
#define EPI_MODE_IN (1<<5)
#define EPI_MODE_OUT (0<<5)
#define EPI_ISO (1<<6)
#define EPI_BULK (0<<6)
#define EPI_AUTO_SET (1<<7)
//OUT_CSR1
#define EPO_OUT_PKT_READY 0x01
#define EPO_OVER_RUN 0x04
#define EPO_DATA_ERROR 0x08
#define EPO_FIFO_FLUSH 0x10
#define EPO_SEND_STALL 0x20
#define EPO_SENT_STALL 0x40
#define EPO_CDT 0x80
#define EPO_WR_BITS (EPO_FIFO_FLUSH|EPO_SEND_STALL|EPO_CDT)
//(EPO_FIFO_FLUSH) is preferred (???)
//OUT_CSR2
#define EPO_OUT_DMA_INT_MASK (1<<5)
#define EPO_ISO (1<<6)
#define EPO_BULK (0<<6)
#define EPO_AUTO_CLR (1<<7)
//USB DMA control register
#define UDMA_IN_RUN_OB (1<<7)
#define UDMA_IGNORE_TTC (1<<7)
#define UDMA_DEMAND_MODE (1<<3)
#define UDMA_OUT_RUN_OB (1<<2)
#define UDMA_OUT_DMA_RUN (1<<2)
#define UDMA_IN_DMA_RUN (1<<1)
#define UDMA_DMA_MODE_EN (1<<0)
#define rEP1_DMA_TTC (rEP1_DMA_TTC_L+(rEP1_DMA_TTC_M<<8)+(rEP1_DMA_TTC_H<<16))
#define rEP2_DMA_TTC (rEP2_DMA_TTC_L+(rEP2_DMA_TTC_M<<8)+(rEP2_DMA_TTC_H<<16))
#define rEP3_DMA_TTC (rEP3_DMA_TTC_L+(rEP3_DMA_TTC_M<<8)+(rEP3_DMA_TTC_H<<16))
#define rEP4_DMA_TTC (rEP4_DMA_TTC_L+(rEP4_DMA_TTC_M<<8)+(rEP4_DMA_TTC_H<<16))
#define ADDR_EP0_FIFO (0x520001c0) //Endpoint 0 FIFO
#define ADDR_EP1_FIFO (0x520001c4) //Endpoint 1 FIFO
#define ADDR_EP2_FIFO (0x520001c8) //Endpoint 2 FIFO
#define ADDR_EP3_FIFO (0x520001cc) //Endpoint 3 FIFO
#define ADDR_EP4_FIFO (0x520001d0) //Endpoint 4 FIFO
//If you chane the packet size, the source code should be changed!!!
#define BULK_PKT_SIZE 64
#define EP0_PKT_SIZE 8
#define EP1_PKT_SIZE BULK_PKT_SIZE
#define EP3_PKT_SIZE BULK_PKT_SIZE
// USB DEVICE DEFINITION END
#ifdef __cplusplus
}
#endif
#endif //__2440ADDR_H__
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