📄 caideng.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\caideng\caideng.rpt
caideng
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 7/ 48( 14%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\caideng\caideng.rpt
caideng
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: e:\eda\caideng\caideng.rpt
caideng
** EQUATIONS **
clk : INPUT;
-- Node name is ':15' = 'cnt0'
-- Equation name is 'cnt0', location is LC7_A16, type is buried.
cnt0 = DFFE(!cnt0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':14' = 'cnt1'
-- Equation name is 'cnt1', location is LC2_A23, type is buried.
cnt1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !cnt0 & cnt1
# cnt0 & !cnt1 & !cnt3
# cnt0 & !cnt1 & cnt2;
-- Node name is ':13' = 'cnt2'
-- Equation name is 'cnt2', location is LC6_A16, type is buried.
cnt2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !cnt0 & cnt2
# !cnt1 & cnt2
# cnt0 & cnt1 & !cnt2;
-- Node name is ':12' = 'cnt3'
-- Equation name is 'cnt3', location is LC1_A23, type is buried.
cnt3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !cnt0 & cnt3
# cnt0 & cnt1 & cnt2 & !cnt3
# !cnt1 & cnt2 & cnt3
# cnt1 & !cnt2 & cnt3;
-- Node name is 'ledout0'
-- Equation name is 'ledout0', type is output
ledout0 = _LC3_A23;
-- Node name is 'ledout1'
-- Equation name is 'ledout1', type is output
ledout1 = _LC4_A23;
-- Node name is 'ledout2'
-- Equation name is 'ledout2', type is output
ledout2 = _LC4_A16;
-- Node name is 'ledout3'
-- Equation name is 'ledout3', type is output
ledout3 = _LC5_A16;
-- Node name is 'ledout4'
-- Equation name is 'ledout4', type is output
ledout4 = _LC2_A16;
-- Node name is 'ledout5'
-- Equation name is 'ledout5', type is output
ledout5 = _LC8_A23;
-- Node name is 'ledout6'
-- Equation name is 'ledout6', type is output
ledout6 = _LC5_A23;
-- Node name is 'ledout7'
-- Equation name is 'ledout7', type is output
ledout7 = _LC6_A23;
-- Node name is 'ledout8'
-- Equation name is 'ledout8', type is output
ledout8 = _LC7_A23;
-- Node name is 'ledout9'
-- Equation name is 'ledout9', type is output
ledout9 = _LC1_A16;
-- Node name is ':196'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ004);
_EQ004 = !cnt0 & !cnt1 & cnt2 & !cnt3;
-- Node name is ':208'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ005);
_EQ005 = cnt0 & cnt1 & !cnt2 & !cnt3;
-- Node name is ':220'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = LCELL( _EQ006);
_EQ006 = !cnt0 & cnt1 & !cnt2 & !cnt3;
-- Node name is ':232'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ007);
_EQ007 = cnt0 & !cnt1 & !cnt2 & !cnt3;
-- Node name is ':244'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ008);
_EQ008 = !cnt0 & !cnt1 & !cnt2 & !cnt3;
-- Node name is ':399'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = LCELL( _EQ009);
_EQ009 = cnt0 & !cnt1 & cnt2 & !cnt3;
-- Node name is ':429'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ010);
_EQ010 = !cnt0 & cnt1 & cnt2 & !cnt3;
-- Node name is ':459'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ011);
_EQ011 = cnt0 & cnt1 & cnt2 & !cnt3;
-- Node name is ':489'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = LCELL( _EQ012);
_EQ012 = !cnt0 & !cnt1 & !cnt2 & cnt3;
-- Node name is ':519'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ013);
_EQ013 = cnt1 & cnt3
# cnt0 & cnt3
# cnt2 & cnt3;
Project Information e:\eda\caideng\caideng.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,439K
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