crc.v

CRC校验码的实现

module  crc (cs,clk,data_in, crc_out,data_out,datacrc_out);
input cs;
input clk;
input  data_in;
output  [5:0]  crc_out;
output  [33:0] data_out;
output  [39:0] datacrc_out;
reg    [5:0]  crc_out;
wire   [33:0] data_out; 
wire   [39:0] datacrc_out;
reg    [33:0]  shift_regsiter;
reg    [39:0]  shift_regsiter0;
always @ (posedge clk)   
   begin
      if ( cs==1)
           crc_out[5:0]=6'b000000;
       else
             begin 
                   crc_out[0]<=crc_out[5] ^ data_in;
                   crc_out[1]<=crc_out[0];
                   crc_out[2]<=crc_out[1] ^ crc_out[5];
                   crc_out[3]<=crc_out[2];
                   crc_out[4]<=crc_out[3];
                   crc_out[5]<=crc_out[4] ^crc_out[5];
              end
    end
always @ (posedge clk)
      begin 
         if (cs==1)
             shift_regsiter=0;
         else 
             shift_regsiter={ shift_regsiter[32:0],data_in};                                                                                                                     
      end
      assign data_out= shift_regsiter; 
always  @ (posedge cs )    
            begin 
             shift_regsiter0[39:0]<= {data_out[33:0],crc_out[5:0]}; 
            end                                                                                                                    
            assign datacrc_out= shift_regsiter0;  
endmodule
module  crc6 (cs,clk,data_in, crc_out,data_out,datacrc_out);
input cs;
input clk;
input  data_in;
output  [5:0]  crc_out;
output  [22:0] data_out;
output  [28:0] datacrc_out;
reg    [5:0]  crc_out;
wire   [22:0] data_out; 
wire   [28:0] datacrc_out;
reg    [22:0]  shift_regsiter;
reg    [28:0]  shift_regsiter0;
always @ (posedge clk)   
   begin
      if ( cs==1)
           crc_out[5:0]=6'b000000;
       else
             begin 
                   crc_out[0]<=crc_out[5] ^ data_in;
                   crc_out[1]<=crc_out[0];
                   crc_out[2]<=crc_out[1] ^ crc_out[5];
                   crc_out[3]<=crc_out[2];
                   crc_out[4]<=crc_out[3];
                   crc_out[5]<=crc_out[4] ^crc_out[5];
              end
    end
always @ (posedge clk)
      begin 
         if (cs==1)
             shift_regsiter=0;
         else 
             shift_regsiter={ shift_regsiter[21:0],data_in};                                                                                                                     
      end
      assign data_out= shift_regsiter; 
always  @ (posedge cs )    
            begin 
             shift_regsiter0[28:0]<= {data_out[22:0],crc_out[5:0]}; 
          // shift_regsiter0[22:0]<= {shift_regsiter,crc_out[5:0]}; 
            end                                                                                                                    
            assign datacrc_out= shift_regsiter0;  
endmodule
module  crc6 (cs,clk,data_in, crc_out,data_out,datacrc_out);
input cs;
input clk;
input  data_in;
output  [5:0]  crc_out;
output  [22:0] data_out;
output  [28:0] datacrc_out;
reg    [5:0]  crc_out;
wire   [22:0] data_out; 
wire   [28:0] datacrc_out;
reg    [22:0]  shift_regsiter;
reg    [28:0]  shift_regsiter0;
always @ (posedge clk)   
   begin
      if ( cs==1)
           crc_out[5:0]=6'b000000;
       else
             begin 
                   crc_out[0]<=crc_out[5] ^ data_in;
                   crc_out[1]<=crc_out[0];
                   crc_out[2]<=crc_out[1] ^ crc_out[5];
                   crc_out[3]<=crc_out[2];
                   crc_out[4]<=crc_out[3];
                   crc_out[5]<=crc_out[4] ^crc_out[5];
              end
    end
always @ (posedge clk)
      begin 
         if (cs==1)
             shift_regsiter=0;
         else 
             shift_regsiter={ shift_regsiter[21:0],data_in};                                                                                                                     
      end
      assign data_out= shift_regsiter; 
always  @ (posedge cs )    
            begin 
             shift_regsiter0[28:0]<= {data_out[22:0],crc_out[5:0]}; 
          // shift_regsiter0[22:0]<= {shift_regsiter,crc_out[5:0]}; 
            end                                                                                                                    
            assign datacrc_out= shift_regsiter0;  
endmodule