872.tan.qmsg

这是一个872进制的eda项目

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register 7490:inst\|19 register 74160:inst2\|7 72.83 MHz 13.73 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 72.83 MHz between source register \"7490:inst\|19\" and destination register \"74160:inst2\|7\" (period= 13.73 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.701 ns + Longest register register " "Info: + Longest register to register delay is 1.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7490:inst\|19 1 REG LC_X8_Y1_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst\|19'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7490:inst|19 } "NODE_NAME" } } { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 512 496 560 592 "19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.114 ns) 0.648 ns inst3 2 COMB LC_X8_Y1_N0 5 " "Info: 2: + IC(0.534 ns) + CELL(0.114 ns) = 0.648 ns; Loc. = LC_X8_Y1_N0; Fanout = 5; COMB Node = 'inst3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.648 ns" { 7490:inst|19 inst3 } "NODE_NAME" } } { "872.bdf" "" { Schematic "C:/altera/lianxi00/872ZUIXIN/872.bdf" { { 144 384 448 192 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 0.944 ns 74160:inst2\|45~3 3 COMB LC_X8_Y1_N1 4 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 0.944 ns; Loc. = LC_X8_Y1_N1; Fanout = 4; COMB Node = '74160:inst2\|45~3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { inst3 74160:inst2|45~3 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74160.bdf" { { 976 1112 1176 1016 "45" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.309 ns) 1.701 ns 74160:inst2\|7 4 REG LC_X8_Y1_N6 4 " "Info: 4: + IC(0.448 ns) + CELL(0.309 ns) = 1.701 ns; Loc. = LC_X8_Y1_N6; Fanout = 4; REG Node = '74160:inst2\|7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.757 ns" { 74160:inst2|45~3 74160:inst2|7 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 31.57 % ) " "Info: Total cell delay = 0.537 ns ( 31.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.164 ns ( 68.43 % ) " "Info: Total interconnect delay = 1.164 ns ( 68.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { 7490:inst|19 inst3 74160:inst2|45~3 74160:inst2|7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.701 ns" { 7490:inst|19 inst3 74160:inst2|45~3 74160:inst2|7 } { 0.000ns 0.534ns 0.182ns 0.448ns } { 0.000ns 0.114ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.903 ns - Smallest " "Info: - Smallest clock skew is -4.903 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.731 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 9; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "872.bdf" "" { Schematic "C:/altera/lianxi00/872ZUIXIN/872.bdf" { { 248 -16 152 264 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.711 ns) 2.731 ns 74160:inst2\|7 2 REG LC_X8_Y1_N6 4 " "Info: 2: + IC(0.551 ns) + CELL(0.711 ns) = 2.731 ns; Loc. = LC_X8_Y1_N6; Fanout = 4; REG Node = '74160:inst2\|7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.262 ns" { CLK 74160:inst2|7 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.82 % ) " "Info: Total cell delay = 2.180 ns ( 79.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.551 ns ( 20.18 % ) " "Info: Total interconnect delay = 0.551 ns ( 20.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.731 ns" { CLK 74160:inst2|7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.731 ns" { CLK CLK~out0 74160:inst2|7 } { 0.000ns 0.000ns 0.551ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.634 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.634 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 9; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "872.bdf" "" { Schematic "C:/altera/lianxi00/872ZUIXIN/872.bdf" { { 248 -16 152 264 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns 7490:inst\|7 2 REG LC_X7_Y2_N2 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y2_N2; Fanout = 7; REG Node = '7490:inst\|7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK 7490:inst|7 } "NODE_NAME" } } { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 144 496 560 224 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.969 ns) + CELL(0.711 ns) 7.634 ns 7490:inst\|19 3 REG LC_X8_Y1_N3 4 " "Info: 3: + IC(3.969 ns) + CELL(0.711 ns) = 7.634 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst\|19'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.680 ns" { 7490:inst|7 7490:inst|19 } "NODE_NAME" } } { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 512 496 560 592 "19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.80 % ) " "Info: Total cell delay = 3.115 ns ( 40.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.519 ns ( 59.20 % ) " "Info: Total interconnect delay = 4.519 ns ( 59.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.634 ns" { CLK 7490:inst|7 7490:inst|19 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.634 ns" { CLK CLK~out0 7490:inst|7 7490:inst|19 } { 0.000ns 0.000ns 0.550ns 3.969ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.731 ns" { CLK 74160:inst2|7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.731 ns" { CLK CLK~out0 74160:inst2|7 } { 0.000ns 0.000ns 0.551ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.634 ns" { CLK 7490:inst|7 7490:inst|19 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.634 ns" { CLK CLK~out0 7490:inst|7 7490:inst|19 } { 0.000ns 0.000ns 0.550ns 3.969ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 512 496 560 592 "19" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 512 496 560 592 "19" "" } } } } { "74160.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { 7490:inst|19 inst3 74160:inst2|45~3 74160:inst2|7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.701 ns" { 7490:inst|19 inst3 74160:inst2|45~3 74160:inst2|7 } { 0.000ns 0.534ns 0.182ns 0.448ns } { 0.000ns 0.114ns 0.114ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.731 ns" { CLK 74160:inst2|7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.731 ns" { CLK CLK~out0 74160:inst2|7 } { 0.000ns 0.000ns 0.551ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.634 ns" { CLK 7490:inst|7 7490:inst|19 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.634 ns" { CLK CLK~out0 7490:inst|7 7490:inst|19 } { 0.000ns 0.000ns 0.550ns 3.969ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK A\[3\] 7490:inst\|19 11.586 ns register " "Info: tco from clock \"CLK\" to destination pin \"A\[3\]\" through register \"7490:inst\|19\" is 11.586 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.634 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.634 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 9; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "872.bdf" "" { Schematic "C:/altera/lianxi00/872ZUIXIN/872.bdf" { { 248 -16 152 264 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns 7490:inst\|7 2 REG LC_X7_Y2_N2 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y2_N2; Fanout = 7; REG Node = '7490:inst\|7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK 7490:inst|7 } "NODE_NAME" } } { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 144 496 560 224 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.969 ns) + CELL(0.711 ns) 7.634 ns 7490:inst\|19 3 REG LC_X8_Y1_N3 4 " "Info: 3: + IC(3.969 ns) + CELL(0.711 ns) = 7.634 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst\|19'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.680 ns" { 7490:inst|7 7490:inst|19 } "NODE_NAME" } } { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 512 496 560 592 "19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.80 % ) " "Info: Total cell delay = 3.115 ns ( 40.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.519 ns ( 59.20 % ) " "Info: Total interconnect delay = 4.519 ns ( 59.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.634 ns" { CLK 7490:inst|7 7490:inst|19 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.634 ns" { CLK CLK~out0 7490:inst|7 7490:inst|19 } { 0.000ns 0.000ns 0.550ns 3.969ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 512 496 560 592 "19" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.728 ns + Longest register pin " "Info: + Longest register to pin delay is 3.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7490:inst\|19 1 REG LC_X8_Y1_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst\|19'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7490:inst|19 } "NODE_NAME" } } { "7490.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7490.bdf" { { 512 496 560 592 "19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.620 ns) + CELL(2.108 ns) 3.728 ns A\[3\] 2 PIN PIN_42 0 " "Info: 2: + IC(1.620 ns) + CELL(2.108 ns) = 3.728 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'A\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.728 ns" { 7490:inst|19 A[3] } "NODE_NAME" } } { "872.bdf" "" { Schematic "C:/altera/lianxi00/872ZUIXIN/872.bdf" { { 584 656 832 600 "A\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 56.55 % ) " "Info: Total cell delay = 2.108 ns ( 56.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.620 ns ( 43.45 % ) " "Info: Total interconnect delay = 1.620 ns ( 43.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.728 ns" { 7490:inst|19 A[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.728 ns" { 7490:inst|19 A[3] } { 0.000ns 1.620ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.634 ns" { CLK 7490:inst|7 7490:inst|19 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.634 ns" { CLK CLK~out0 7490:inst|7 7490:inst|19 } { 0.000ns 0.000ns 0.550ns 3.969ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.728 ns" { 7490:inst|19 A[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.728 ns" { 7490:inst|19 A[3] } { 0.000ns 1.620ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 19 13:42:41 2009 " "Info: Processing ended: Thu Mar 19 13:42:41 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}