872.map.rpt

这是一个872进制的eda项目

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                            ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                            ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+
; 872.bdf                          ; yes             ; User Block Diagram/Schematic File  ; C:/altera/lianxi00/872ZUIXIN/872.bdf                    ;
; 7490.bdf                         ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/others/maxplus2/7490.bdf  ;
; 74160.bdf                        ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/others/maxplus2/74160.bdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 17    ;
;     -- Combinational with no register       ; 5     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 12    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 7     ;
;     -- 3 input functions                    ; 4     ;
;     -- 2 input functions                    ; 5     ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 17    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 12    ;
;                                             ;       ;
; Total registers                             ; 12    ;
; I/O pins                                    ; 13    ;
; Maximum fan-out node                        ; inst4 ;
; Maximum fan-out                             ; 9     ;
; Total fan-out                               ; 87    ;
; Average fan-out                             ; 2.90  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |872                       ; 17 (4)      ; 12           ; 0           ; 0    ; 13   ; 0            ; 5 (4)        ; 0 (0)             ; 12 (0)           ; 0 (0)           ; 0 (0)      ; |872                ;
;    |74160:inst1|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |872|74160:inst1    ;
;    |74160:inst2|           ; 5 (5)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |872|74160:inst2    ;
;    |7490:inst|             ; 4 (4)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |872|7490:inst      ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 12    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 12    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Mar 19 13:42:34 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 872 -c 872
Info: Found 1 design units, including 1 entities, in source file 872.bdf
    Info: Found entity 1: 872
Info: Elaborating entity "872" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/7490.bdf
    Info: Found entity 1: 7490
Info: Elaborating entity "7490" for hierarchy "7490:inst"
Info: Elaborated megafunction instantiation "7490:inst"
Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/74160.bdf
    Info: Found entity 1: 74160
Info: Elaborating entity "74160" for hierarchy "74160:inst1"
Info: Elaborated megafunction instantiation "74160:inst1"
Info: Implemented 30 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 12 output pins
    Info: Implemented 17 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Mar 19 13:42:35 2009
    Info: Elapsed time: 00:00:01