872.tan.rpt

这是一个872进制的eda项目

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst2|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.908 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst2|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.907 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|9 ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.741 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.727 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.726 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.642 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.625 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst2|6 ; CLK        ; CLK      ; None                        ; None                      ; 1.623 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.622 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.621 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.461 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|6 ; CLK        ; CLK      ; None                        ; None                      ; 1.395 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst1|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.335 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst2|6 ; CLK        ; CLK      ; None                        ; None                      ; 1.332 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst1|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.329 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 7490:inst|11  ; 7490:inst|19  ; CLK        ; CLK      ; None                        ; None                      ; 1.284 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|7 ; 74160:inst2|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.284 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|8 ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.283 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|7 ; 74160:inst2|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.282 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|7 ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.259 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|7 ; 74160:inst1|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.134 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|7 ; 74160:inst1|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.133 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|6 ; CLK        ; CLK      ; None                        ; None                      ; 1.133 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 7490:inst|19  ; 7490:inst|11  ; CLK        ; CLK      ; None                        ; None                      ; 1.094 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 7490:inst|11  ; 7490:inst|14  ; CLK        ; CLK      ; None                        ; None                      ; 1.083 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 7490:inst|14  ; 7490:inst|19  ; CLK        ; CLK      ; None                        ; None                      ; 1.071 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|8 ; 74160:inst2|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.037 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|9 ; 74160:inst2|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.033 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|8 ; 74160:inst1|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.030 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 7490:inst|14  ; 7490:inst|14  ; CLK        ; CLK      ; None                        ; None                      ; 1.020 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 7490:inst|11  ; 7490:inst|11  ; CLK        ; CLK      ; None                        ; None                      ; 1.016 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 7490:inst|7   ; 7490:inst|7   ; CLK        ; CLK      ; None                        ; None                      ; 1.014 ns                ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+---------------+------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To   ; From Clock ;
+-------+--------------+------------+---------------+------+------------+
; N/A   ; None         ; 11.586 ns  ; 7490:inst|19  ; A[3] ; CLK        ;
; N/A   ; None         ; 11.585 ns  ; 7490:inst|14  ; A[2] ; CLK        ;
; N/A   ; None         ; 11.576 ns  ; 7490:inst|11  ; A[1] ; CLK        ;
; N/A   ; None         ; 7.794 ns   ; 74160:inst2|9 ; C[3] ; CLK        ;
; N/A   ; None         ; 7.777 ns   ; 74160:inst2|8 ; C[2] ; CLK        ;
; N/A   ; None         ; 6.739 ns   ; 7490:inst|7   ; A[0] ; CLK        ;
; N/A   ; None         ; 6.696 ns   ; 74160:inst2|7 ; C[1] ; CLK        ;
; N/A   ; None         ; 6.680 ns   ; 74160:inst2|6 ; C[0] ; CLK        ;
; N/A   ; None         ; 6.377 ns   ; 74160:inst1|6 ; B[0] ; CLK        ;
; N/A   ; None         ; 6.367 ns   ; 74160:inst1|9 ; B[3] ; CLK        ;
; N/A   ; None         ; 6.365 ns   ; 74160:inst1|8 ; B[2] ; CLK        ;
; N/A   ; None         ; 6.361 ns   ; 74160:inst1|7 ; B[1] ; CLK        ;
+-------+--------------+------------+---------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Mar 19 13:42:41 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 872 -c 872 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "7490:inst|7" as buffer
Info: Clock "CLK" has Internal fmax of 72.83 MHz between source register "7490:inst|19" and destination register "74160:inst2|7" (period= 13.73 ns)
    Info: + Longest register to register delay is 1.701 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst|19'
        Info: 2: + IC(0.534 ns) + CELL(0.114 ns) = 0.648 ns; Loc. = LC_X8_Y1_N0; Fanout = 5; COMB Node = 'inst3'
        Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 0.944 ns; Loc. = LC_X8_Y1_N1; Fanout = 4; COMB Node = '74160:inst2|45~3'
        Info: 4: + IC(0.448 ns) + CELL(0.309 ns) = 1.701 ns; Loc. = LC_X8_Y1_N6; Fanout = 4; REG Node = '74160:inst2|7'
        Info: Total cell delay = 0.537 ns ( 31.57 % )
        Info: Total interconnect delay = 1.164 ns ( 68.43 % )
    Info: - Smallest clock skew is -4.903 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.731 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.551 ns) + CELL(0.711 ns) = 2.731 ns; Loc. = LC_X8_Y1_N6; Fanout = 4; REG Node = '74160:inst2|7'
            Info: Total cell delay = 2.180 ns ( 79.82 % )
            Info: Total interconnect delay = 0.551 ns ( 20.18 % )
        Info: - Longest clock path from clock "CLK" to source register is 7.634 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y2_N2; Fanout = 7; REG Node = '7490:inst|7'
            Info: 3: + IC(3.969 ns) + CELL(0.711 ns) = 7.634 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst|19'
            Info: Total cell delay = 3.115 ns ( 40.80 % )
            Info: Total interconnect delay = 4.519 ns ( 59.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tco from clock "CLK" to destination pin "A[3]" through register "7490:inst|19" is 11.586 ns
    Info: + Longest clock path from clock "CLK" to source register is 7.634 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y2_N2; Fanout = 7; REG Node = '7490:inst|7'
        Info: 3: + IC(3.969 ns) + CELL(0.711 ns) = 7.634 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst|19'
        Info: Total cell delay = 3.115 ns ( 40.80 % )
        Info: Total interconnect delay = 4.519 ns ( 59.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.728 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y1_N3; Fanout = 4; REG Node = '7490:inst|19'
        Info: 2: + IC(1.620 ns) + CELL(2.108 ns) = 3.728 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'A[3]'
        Info: Total cell delay = 2.108 ns ( 56.55 % )
        Info: Total interconnect delay = 1.620 ns ( 43.45 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Mar 19 13:42:41 2009
    Info: Elapsed time: 00:00:00