872.tan.rpt

这是一个872进制的eda项目

Timing Analyzer report for 872
Thu Mar 19 13:42:41 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                       ;
+------------------------------+-------+---------------+----------------------------------+--------------+---------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From         ; To            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------+---------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 11.586 ns                        ; 7490:inst|19 ; A[3]          ; CLK        ; --       ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 72.83 MHz ( period = 13.730 ns ) ; 7490:inst|19 ; 74160:inst2|7 ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;              ;               ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------+---------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                 ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From          ; To            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 72.83 MHz ( period = 13.730 ns )               ; 7490:inst|19  ; 74160:inst2|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.701 ns                ;
; N/A   ; 72.84 MHz ( period = 13.728 ns )               ; 7490:inst|19  ; 74160:inst2|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.700 ns                ;
; N/A   ; 75.72 MHz ( period = 13.206 ns )               ; 7490:inst|19  ; 74160:inst1|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.439 ns                ;
; N/A   ; 75.75 MHz ( period = 13.202 ns )               ; 7490:inst|19  ; 74160:inst1|8 ; CLK        ; CLK      ; None                        ; None                      ; 1.437 ns                ;
; N/A   ; 75.76 MHz ( period = 13.200 ns )               ; 7490:inst|19  ; 74160:inst2|6 ; CLK        ; CLK      ; None                        ; None                      ; 1.436 ns                ;
; N/A   ; 75.77 MHz ( period = 13.198 ns )               ; 7490:inst|19  ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.435 ns                ;
; N/A   ; 75.79 MHz ( period = 13.194 ns )               ; 7490:inst|19  ; 74160:inst1|7 ; CLK        ; CLK      ; None                        ; None                      ; 1.433 ns                ;
; N/A   ; 79.87 MHz ( period = 12.520 ns )               ; 7490:inst|19  ; 74160:inst1|6 ; CLK        ; CLK      ; None                        ; None                      ; 1.096 ns                ;
; N/A   ; 169.49 MHz ( period = 5.900 ns )               ; 7490:inst|7   ; 74160:inst2|7 ; CLK        ; CLK      ; None                        ; None                      ; 2.690 ns                ;
; N/A   ; 169.55 MHz ( period = 5.898 ns )               ; 7490:inst|7   ; 74160:inst2|8 ; CLK        ; CLK      ; None                        ; None                      ; 2.689 ns                ;
; N/A   ; 186.01 MHz ( period = 5.376 ns )               ; 7490:inst|7   ; 74160:inst1|9 ; CLK        ; CLK      ; None                        ; None                      ; 2.428 ns                ;
; N/A   ; 186.15 MHz ( period = 5.372 ns )               ; 7490:inst|7   ; 74160:inst1|8 ; CLK        ; CLK      ; None                        ; None                      ; 2.426 ns                ;
; N/A   ; 186.22 MHz ( period = 5.370 ns )               ; 7490:inst|7   ; 74160:inst2|6 ; CLK        ; CLK      ; None                        ; None                      ; 2.425 ns                ;
; N/A   ; 186.29 MHz ( period = 5.368 ns )               ; 7490:inst|7   ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 2.424 ns                ;
; N/A   ; 186.43 MHz ( period = 5.364 ns )               ; 7490:inst|7   ; 74160:inst1|7 ; CLK        ; CLK      ; None                        ; None                      ; 2.422 ns                ;
; N/A   ; 251.64 MHz ( period = 3.974 ns )               ; 7490:inst|7   ; 74160:inst1|6 ; CLK        ; CLK      ; None                        ; None                      ; 1.727 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|8 ; 74160:inst1|9 ; CLK        ; CLK      ; None                        ; None                      ; 2.339 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst2|7 ; CLK        ; CLK      ; None                        ; None                      ; 2.236 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst2|8 ; CLK        ; CLK      ; None                        ; None                      ; 2.235 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|7 ; 74160:inst1|9 ; CLK        ; CLK      ; None                        ; None                      ; 2.139 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst2|9 ; CLK        ; CLK      ; None                        ; None                      ; 1.970 ns                ;