sdram_tb.map.eqn

SDRAM IPCore控制程序源代码。 请问有无usb原码

--operation mode is normal

C1L701 = B1_addr_r[17] & C1_activeRow_r[0][9] & (B1_addr_r[11] $ !C1_activeRow_r[0][3]) # !B1_addr_r[17] & !C1_activeRow_r[0][9] & (B1_addr_r[11] $ !C1_activeRow_r[0][3]);


--B1_addr_r[16] is memTest:memt|addr_r[16]
--operation mode is arithmetic

B1_addr_r[16]_carry_eqn = B1L53;
B1_addr_r[16]_lut_out = B1_addr_r[16] $ (!B1_addr_r[16]_carry_eqn);
B1_addr_r[16] = DFFEAS(B1_addr_r[16]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L73 is memTest:memt|addr_r[16]~329
--operation mode is arithmetic

B1L73 = CARRY(B1_addr_r[16] & (!B1L53));


--B1_addr_r[8] is memTest:memt|addr_r[8]
--operation mode is arithmetic

B1_addr_r[8]_carry_eqn = B1L81;
B1_addr_r[8]_lut_out = B1_addr_r[8] $ (!B1_addr_r[8]_carry_eqn);
B1_addr_r[8] = DFFEAS(B1_addr_r[8]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L02 is memTest:memt|addr_r[8]~333
--operation mode is arithmetic

B1L02 = CARRY(B1_addr_r[8] & (!B1L81));


--C1_activeRow_r[0][0] is sdramCntl:sdram1|activeRow_r[0][0]
--operation mode is normal

C1_activeRow_r[0][0]_lut_out = B1_addr_r[8];
C1_activeRow_r[0][0] = DFFEAS(C1_activeRow_r[0][0]_lut_out, clk, VCC, , C1L8, , , , );


--C1_activeRow_r[0][8] is sdramCntl:sdram1|activeRow_r[0][8]
--operation mode is normal

C1_activeRow_r[0][8]_lut_out = B1_addr_r[16];
C1_activeRow_r[0][8] = DFFEAS(C1_activeRow_r[0][8]_lut_out, clk, VCC, , C1L8, , , , );


--C1L801 is sdramCntl:sdram1|combinatorial~154
--operation mode is normal

C1L801 = B1_addr_r[16] & C1_activeRow_r[0][8] & (B1_addr_r[8] $ !C1_activeRow_r[0][0]) # !B1_addr_r[16] & !C1_activeRow_r[0][8] & (B1_addr_r[8] $ !C1_activeRow_r[0][0]);


--B1_addr_r[13] is memTest:memt|addr_r[13]
--operation mode is arithmetic

B1_addr_r[13]_carry_eqn = B1L92;
B1_addr_r[13]_lut_out = B1_addr_r[13] $ (B1_addr_r[13]_carry_eqn);
B1_addr_r[13] = DFFEAS(B1_addr_r[13]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L13 is memTest:memt|addr_r[13]~337
--operation mode is arithmetic

B1L13 = CARRY(!B1L92 # !B1_addr_r[13]);


--B1_addr_r[20] is memTest:memt|addr_r[20]
--operation mode is arithmetic

B1_addr_r[20]_carry_eqn = B1L34;
B1_addr_r[20]_lut_out = B1_addr_r[20] $ (!B1_addr_r[20]_carry_eqn);
B1_addr_r[20] = DFFEAS(B1_addr_r[20]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L54 is memTest:memt|addr_r[20]~341
--operation mode is arithmetic

B1L54 = CARRY(B1_addr_r[20] & (!B1L34));


--C1_activeBank_r[0] is sdramCntl:sdram1|activeBank_r[0]
--operation mode is normal

C1_activeBank_r[0]_lut_out = B1_addr_r[20];
C1_activeBank_r[0] = DFFEAS(C1_activeBank_r[0]_lut_out, clk, VCC, , C1L8, , , , );


--C1_activeRow_r[0][5] is sdramCntl:sdram1|activeRow_r[0][5]
--operation mode is normal

C1_activeRow_r[0][5]_lut_out = B1_addr_r[13];
C1_activeRow_r[0][5] = DFFEAS(C1_activeRow_r[0][5]_lut_out, clk, VCC, , C1L8, , , , );


--C1L901 is sdramCntl:sdram1|combinatorial~155
--operation mode is normal

C1L901 = B1_addr_r[13] & C1_activeRow_r[0][5] & (B1_addr_r[20] $ !C1_activeBank_r[0]) # !B1_addr_r[13] & !C1_activeRow_r[0][5] & (B1_addr_r[20] $ !C1_activeBank_r[0]);


--B1_addr_r[9] is memTest:memt|addr_r[9]
--operation mode is arithmetic

B1_addr_r[9]_carry_eqn = B1L02;
B1_addr_r[9]_lut_out = B1_addr_r[9] $ (B1_addr_r[9]_carry_eqn);
B1_addr_r[9] = DFFEAS(B1_addr_r[9]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L32 is memTest:memt|addr_r[9]~345
--operation mode is arithmetic

B1L32 = CARRY(!B1L02 # !B1_addr_r[9]);


--B1_addr_r[19] is memTest:memt|addr_r[19]
--operation mode is arithmetic

B1_addr_r[19]_carry_eqn = B1L14;
B1_addr_r[19]_lut_out = B1_addr_r[19] $ (B1_addr_r[19]_carry_eqn);
B1_addr_r[19] = DFFEAS(B1_addr_r[19]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L34 is memTest:memt|addr_r[19]~349
--operation mode is arithmetic

B1L34 = CARRY(!B1L14 # !B1_addr_r[19]);


--C1_activeRow_r[0][11] is sdramCntl:sdram1|activeRow_r[0][11]
--operation mode is normal

C1_activeRow_r[0][11]_lut_out = B1_addr_r[19];
C1_activeRow_r[0][11] = DFFEAS(C1_activeRow_r[0][11]_lut_out, clk, VCC, , C1L8, , , , );


--C1_activeRow_r[0][1] is sdramCntl:sdram1|activeRow_r[0][1]
--operation mode is normal

C1_activeRow_r[0][1]_lut_out = B1_addr_r[9];
C1_activeRow_r[0][1] = DFFEAS(C1_activeRow_r[0][1]_lut_out, clk, VCC, , C1L8, , , , );


--C1L011 is sdramCntl:sdram1|combinatorial~156
--operation mode is normal

C1L011 = B1_addr_r[9] & C1_activeRow_r[0][1] & (B1_addr_r[19] $ !C1_activeRow_r[0][11]) # !B1_addr_r[9] & !C1_activeRow_r[0][1] & (B1_addr_r[19] $ !C1_activeRow_r[0][11]);


--C1L111 is sdramCntl:sdram1|combinatorial~157
--operation mode is normal

C1L111 = C1L701 & C1L801 & C1L901 & C1L011;


--B1_addr_r[18] is memTest:memt|addr_r[18]
--operation mode is arithmetic

B1_addr_r[18]_carry_eqn = B1L93;
B1_addr_r[18]_lut_out = B1_addr_r[18] $ (!B1_addr_r[18]_carry_eqn);
B1_addr_r[18] = DFFEAS(B1_addr_r[18]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L14 is memTest:memt|addr_r[18]~353
--operation mode is arithmetic

B1L14 = CARRY(B1_addr_r[18] & (!B1L93));


--B1_addr_r[12] is memTest:memt|addr_r[12]
--operation mode is arithmetic

B1_addr_r[12]_carry_eqn = B1L72;
B1_addr_r[12]_lut_out = B1_addr_r[12] $ (!B1_addr_r[12]_carry_eqn);
B1_addr_r[12] = DFFEAS(B1_addr_r[12]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L92 is memTest:memt|addr_r[12]~357
--operation mode is arithmetic

B1L92 = CARRY(B1_addr_r[12] & (!B1L72));


--C1_activeRow_r[0][4] is sdramCntl:sdram1|activeRow_r[0][4]
--operation mode is normal

C1_activeRow_r[0][4]_lut_out = B1_addr_r[12];
C1_activeRow_r[0][4] = DFFEAS(C1_activeRow_r[0][4]_lut_out, clk, VCC, , C1L8, , , , );


--C1_activeRow_r[0][10] is sdramCntl:sdram1|activeRow_r[0][10]
--operation mode is normal

C1_activeRow_r[0][10]_lut_out = B1_addr_r[18];
C1_activeRow_r[0][10] = DFFEAS(C1_activeRow_r[0][10]_lut_out, clk, VCC, , C1L8, , , , );


--C1L211 is sdramCntl:sdram1|combinatorial~158
--operation mode is normal

C1L211 = B1_addr_r[18] & C1_activeRow_r[0][10] & (B1_addr_r[12] $ !C1_activeRow_r[0][4]) # !B1_addr_r[18] & !C1_activeRow_r[0][10] & (B1_addr_r[12] $ !C1_activeRow_r[0][4]);


--B1_addr_r[15] is memTest:memt|addr_r[15]
--operation mode is arithmetic

B1_addr_r[15]_carry_eqn = B1L33;
B1_addr_r[15]_lut_out = B1_addr_r[15] $ (B1_addr_r[15]_carry_eqn);
B1_addr_r[15] = DFFEAS(B1_addr_r[15]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L53 is memTest:memt|addr_r[15]~361
--operation mode is arithmetic

B1L53 = CARRY(!B1L33 # !B1_addr_r[15]);


--B1_addr_r[10] is memTest:memt|addr_r[10]
--operation mode is arithmetic

B1_addr_r[10]_carry_eqn = B1L32;
B1_addr_r[10]_lut_out = B1_addr_r[10] $ (!B1_addr_r[10]_carry_eqn);
B1_addr_r[10] = DFFEAS(B1_addr_r[10]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L52 is memTest:memt|addr_r[10]~365
--operation mode is arithmetic

B1L52 = CARRY(B1_addr_r[10] & (!B1L32));


--C1_activeRow_r[0][2] is sdramCntl:sdram1|activeRow_r[0][2]
--operation mode is normal

C1_activeRow_r[0][2]_lut_out = B1_addr_r[10];
C1_activeRow_r[0][2] = DFFEAS(C1_activeRow_r[0][2]_lut_out, clk, VCC, , C1L8, , , , );


--C1_activeRow_r[0][7] is sdramCntl:sdram1|activeRow_r[0][7]
--operation mode is normal

C1_activeRow_r[0][7]_lut_out = B1_addr_r[15];
C1_activeRow_r[0][7] = DFFEAS(C1_activeRow_r[0][7]_lut_out, clk, VCC, , C1L8, , , , );


--C1L311 is sdramCntl:sdram1|combinatorial~159
--operation mode is normal

C1L311 = B1_addr_r[15] & C1_activeRow_r[0][7] & (B1_addr_r[10] $ !C1_activeRow_r[0][2]) # !B1_addr_r[15] & !C1_activeRow_r[0][7] & (B1_addr_r[10] $ !C1_activeRow_r[0][2]);


--C1_activeFlag_r[0] is sdramCntl:sdram1|activeFlag_r[0]
--operation mode is normal

C1_activeFlag_r[0]_lut_out = C1L903 # !C1_state_r.rw & !C1_state_r.selfrefresh & C1_state_r.activate;
C1_activeFlag_r[0] = DFFEAS(C1_activeFlag_r[0]_lut_out, clk, rst_n, , !C1L502, , , , );


--B1_addr_r[21] is memTest:memt|addr_r[21]
--operation mode is arithmetic

B1_addr_r[21]_carry_eqn = B1L54;
B1_addr_r[21]_lut_out = B1_addr_r[21] $ (B1_addr_r[21]_carry_eqn);
B1_addr_r[21] = DFFEAS(B1_addr_r[21]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L74 is memTest:memt|addr_r[21]~369
--operation mode is arithmetic

B1L74 = CARRY(!B1L54 # !B1_addr_r[21]);


--C1_activeBank_r[1] is sdramCntl:sdram1|activeBank_r[1]
--operation mode is normal

C1_activeBank_r[1]_lut_out = B1_addr_r[21];
C1_activeBank_r[1] = DFFEAS(C1_activeBank_r[1]_lut_out, clk, VCC, , C1L8, , , , );


--B1_addr_r[14] is memTest:memt|addr_r[14]
--operation mode is arithmetic

B1_addr_r[14]_carry_eqn = B1L13;
B1_addr_r[14]_lut_out = B1_addr_r[14] $ (!B1_addr_r[14]_carry_eqn);
B1_addr_r[14] = DFFEAS(B1_addr_r[14]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L33 is memTest:memt|addr_r[14]~373
--operation mode is arithmetic

B1L33 = CARRY(B1_addr_r[14] & (!B1L13));


--C1_activeRow_r[0][6] is sdramCntl:sdram1|activeRow_r[0][6]
--operation mode is normal

C1_activeRow_r[0][6]_lut_out = B1_addr_r[14];
C1_activeRow_r[0][6] = DFFEAS(C1_activeRow_r[0][6]_lut_out, clk, VCC, , C1L8, , , , );


--C1L151 is sdramCntl:sdram1|nequal~8
--operation mode is normal

C1L151 = B1_addr_r[14] $ C1_activeRow_r[0][6];


--C1L411 is sdramCntl:sdram1|combinatorial~160
--operation mode is normal

C1L411 = C1_activeFlag_r[0] & !C1L151 & (B1_addr_r[21] $ !C1_activeBank_r[1]);


--C1L601 is sdramCntl:sdram1|combinatorial~1
--operation mode is normal

C1L601 = C1L111 & C1L211 & C1L311 & C1L411;


--C1L723 is sdramCntl:sdram1|state_x.rw~297
--operation mode is normal

C1L723 = !C1L591 & (C1L243 & C1L601 # !C1L243 & (C1L002));


--C1_rdPipeline_r[4] is sdramCntl:sdram1|rdPipeline_r[4]
--operation mode is normal

C1_rdPipeline_r[4]_lut_out = C1L381 & C1L69 & !B1L45 & !C1L502;
C1_rdPipeline_r[4] = DFFEAS(C1_rdPipeline_r[4]_lut_out, clk, rst_n, , , , , , );


--C1_rdPipeline_r[3] is sdramCntl:sdram1|rdPipeline_r[3]
--operation mode is normal

C1_rdPipeline_r[3]_lut_out = C1_rdPipeline_r[4];
C1_rdPipeline_r[3] = DFFEAS(C1_rdPipeline_r[3]_lut_out, clk, rst_n, , , , , , );


--C1_rdPipeline_r[2] is sdramCntl:sdram1|rdPipeline_r[2]
--operation mode is normal

C1_rdPipeline_r[2]_lut_out = C1_rdPipeline_r[3];
C1_rdPipeline_r[2] = DFFEAS(C1_rdPipeline_r[2]_lut_out, clk, rst_n, , , , , , );


--C1_rdPipeline_r[1] is sdramCntl:sdram1|rdPipeline_r[1]
--operation mode is normal

C1_rdPipeline_r[1]_lut_out = C1_rdPipeline_r[2];
C1_rdPipeline_r[1] = DFFEAS(C1_rdPipeline_r[1]_lut_out, clk, rst_n, , , , , , );


--C1L381 is sdramCntl:sdram1|rdPending~33
--operation mode is normal

C1L381 = !C1_rdPipeline_r[4] & !C1_rdPipeline_r[3] & !C1_rdPipeline_r[2] & !C1_rdPipeline_r[1];


--C1_rasTimer_r[1] is sdramCntl:sdram1|rasTimer_r[1]
--operation mode is normal

C1_rasTimer_r[1]_lut_out = C1_rasTimer_r[1] & (C1_rasTimer_r[0] # C1_state_r.activate & !C1L502) # !C1_rasTimer_r[1] & (C1_state_r.activate & !C1L502);
C1_rasTimer_r[1] = DFFEAS(C1_rasTimer_r[1]_lut_out, clk, rst_n, , , , , , );


--C1_rasTimer_r[0] is sdramCntl:sdram1|rasTimer_r[0]
--operation mode is normal

C1_rasTimer_r[0]_lut_out = C1_state_r.activate & (C1_rasTimer_r[1] & !C1_rasTimer_r[0] # !C1L502) # !C1_state_r.activate & C1_rasTimer_r[1] & (!C1_rasTimer_r[0]);
C1_rasTimer_r[0] = DFFEAS(C1_rasTimer_r[0]_lut_out, clk, rst_n, , , , , , );


--C1L511 is sdramCntl:sdram1|combinatorial~161
--operation mode is normal

C1L511 = C1L381 & !C1_wrPipeline_r[0] & !C1_rasTimer_r[1] & !C1_rasTimer_r[0];


--C1L823 is sdramCntl:sdram1|state_x.rw~298
--operation mode is normal

C1L823 = C1_state_r.rw & !C1L511 & (C1_state_r.initrfsh # !C1L723);


--C1L491 is sdramCntl:sdram1|reduce_nor~87
--operation mode is normal

C1L491 = C1L191 & C1L291 & C1L391;


--C1L123 is sdramCntl:sdram1|state_x.initsetmode~199
--operation mode is normal

C1L123 = C1_state_r.initrfsh & (!C1L491 # !C1_rfshCntr_r[0]);


--C1L223 is sdramCntl:sdram1|state_x.initsetmode~200
--operation mode is normal

C1L223 = !C1L502 & (C1L002 # C1L243 # !C1_state_r.selfrefresh);


--C1L323 is sdramCntl:sdram1|state_x.initsetmode~201
--operation mode is normal

C1L323 = C1L223 & (!C1L723 # !C1L243 # !C1_state_r.rw);


--C1L923 is sdramCntl:sdram1|state_x.rw~299
--operation mode is normal

C1L923 = !C1L823 & C1L323 & (C1_state_r.rw # !C1L123);


--C1L602 is sdramCntl:sdram1|reduce_or~413
--operation mode is normal

C1L602 = C1L102 # C1L202;


--C1L702 is sdramCntl:sdram1|reduce_or~414
--operation mode is normal

C1L702 = C1L302 # C1_timer_r[1] # C1_timer_r[0];


--C1L12 is sdramCntl:sdram1|add~2357
--operation mode is normal

C1L12 = C1_rfshCntr_r[0] & (C1L602 # C1L702 # !C1_state_r.initpchg);


--C1L023 is sdramCntl:sdram1|state_x.initrfsh~20
--operation mode is normal

C1L023 = !C1_state_r.activate & !C1_state_r.initsetmode;


--C1L003 is sdramCntl:sdram1|Select~912
--operation mode is normal

C1L003 = !C1_state_r.rw & !C1_state_r.selfrefresh;


--C1_refTimer_r[7] is sdramCntl:sdram1|refTimer_r[7]
--operation mode is normal

C1_refTimer_r[7]_lut_out = C1L36 & C1L012;
C1_refTimer_r[7] = DFFEAS(C1_refTimer_r[7]_lut_out, clk, rst_n, , , , , , );


--C1_refTimer_r[6] is sdramCntl:sdram1|refTimer_r[6]
--operation mode is normal

C1_refTimer_r[6]_lut_out = C1L56 & C1L012;
C1_refTimer_r[6] = DFFEAS(C1_refTimer_r[6]_lut_out, clk, rst_n, , , , , , );


--C1_refTimer_r[5] is sdramCntl:sdram1|refTimer_r[5]
--operation mode is normal

C1_refTimer_r[5]_lut_out = C1L76 & C1L012;
C1_refTimer_r[5] = DFFEAS(C1_refTimer_r[5]_lut_out, clk, rst_n, , , , , , );


--C1_refTimer_r[4] is sdramCntl:sdram1|refTimer_r[4]