sdram_tb.map.eqn

SDRAM IPCore控制程序源代码。 请问有无usb原码

--C1L002 is sdramCntl:sdram1|reduce_or~407
--operation mode is normal

C1L002 = C1L691 # C1L791 # C1L891 # C1L991;


--C1L433 is sdramCntl:sdram1|status[0]~796
--operation mode is normal

C1L433 = C1_state_r.rw & (C1L333 # B1L45 & C1L002);


--C1_state_r.initwait is sdramCntl:sdram1|state_r.initwait
--operation mode is normal

C1_state_r.initwait_lut_out = VCC;
C1_state_r.initwait = DFFEAS(C1_state_r.initwait_lut_out, clk, rst_n, , C1L523, , , , );


--C1_state_r.initrfsh is sdramCntl:sdram1|state_r.initrfsh
--operation mode is normal

C1_state_r.initrfsh_lut_out = C1_state_r.initpchg & !C1_state_r.refreshrow & !C1_state_r.activate & !C1_state_r.initsetmode;
C1_state_r.initrfsh = DFFEAS(C1_state_r.initrfsh_lut_out, clk, rst_n, , C1L923, , , , );


--C1_state_r.refreshrow is sdramCntl:sdram1|state_r.refreshrow
--operation mode is normal

C1_state_r.refreshrow_lut_out = C1_state_r.rw & C1L381 & C1L611 & C1L591;
C1_state_r.refreshrow = DFFEAS(C1_state_r.refreshrow_lut_out, clk, rst_n, , !C1L502, , , , );


--C1L02 is sdramCntl:sdram1|add~2356
--operation mode is normal

C1L02 = !C1_state_r.initrfsh & !C1_state_r.refreshrow;


--C1_timer_r[13] is sdramCntl:sdram1|timer_r[13]
--operation mode is normal

C1_timer_r[13]_lut_out = !C1L063 & (C1L502 & C1L63 # !C1L502 & (!C1_state_r.initwait));
C1_timer_r[13] = DFFEAS(C1_timer_r[13]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[12] is sdramCntl:sdram1|timer_r[12]
--operation mode is normal

C1_timer_r[12]_lut_out = C1L73 & C1L502 & (!C1L063);
C1_timer_r[12] = DFFEAS(C1_timer_r[12]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[11] is sdramCntl:sdram1|timer_r[11]
--operation mode is normal

C1_timer_r[11]_lut_out = C1L93 & C1L502 & (!C1L063);
C1_timer_r[11] = DFFEAS(C1_timer_r[11]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[10] is sdramCntl:sdram1|timer_r[10]
--operation mode is normal

C1_timer_r[10]_lut_out = !C1L063 & (C1L502 & C1L14 # !C1L502 & (!C1_state_r.initwait));
C1_timer_r[10] = DFFEAS(C1_timer_r[10]_lut_out, clk, rst_n, , , , , , );


--C1L102 is sdramCntl:sdram1|reduce_or~408
--operation mode is normal

C1L102 = C1_timer_r[13] # C1_timer_r[12] # C1_timer_r[11] # C1_timer_r[10];


--C1_timer_r[9] is sdramCntl:sdram1|timer_r[9]
--operation mode is normal

C1_timer_r[9]_lut_out = !C1L063 & (C1L502 & C1L34 # !C1L502 & (!C1_state_r.initwait));
C1_timer_r[9] = DFFEAS(C1_timer_r[9]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[8] is sdramCntl:sdram1|timer_r[8]
--operation mode is normal

C1_timer_r[8]_lut_out = !C1L063 & (C1L502 & C1L54 # !C1L502 & (!C1_state_r.initwait));
C1_timer_r[8] = DFFEAS(C1_timer_r[8]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[7] is sdramCntl:sdram1|timer_r[7]
--operation mode is normal

C1_timer_r[7]_lut_out = C1L74 & C1L502 & (!C1L063);
C1_timer_r[7] = DFFEAS(C1_timer_r[7]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[6] is sdramCntl:sdram1|timer_r[6]
--operation mode is normal

C1_timer_r[6]_lut_out = C1L94 & C1L502 & (!C1L063);
C1_timer_r[6] = DFFEAS(C1_timer_r[6]_lut_out, clk, rst_n, , , , , , );


--C1L202 is sdramCntl:sdram1|reduce_or~409
--operation mode is normal

C1L202 = C1_timer_r[9] # C1_timer_r[8] # C1_timer_r[7] # C1_timer_r[6];


--C1_timer_r[5] is sdramCntl:sdram1|timer_r[5]
--operation mode is normal

C1_timer_r[5]_lut_out = C1L15 & C1L502 & (!C1L063);
C1_timer_r[5] = DFFEAS(C1_timer_r[5]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[4] is sdramCntl:sdram1|timer_r[4]
--operation mode is normal

C1_timer_r[4]_lut_out = !C1L063 & (C1L502 & C1L35 # !C1L502 & (!C1_state_r.initwait));
C1_timer_r[4] = DFFEAS(C1_timer_r[4]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[3] is sdramCntl:sdram1|timer_r[3]
--operation mode is normal

C1_timer_r[3]_lut_out = C1L55 & C1L502 & (!C1L063);
C1_timer_r[3] = DFFEAS(C1_timer_r[3]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[2] is sdramCntl:sdram1|timer_r[2]
--operation mode is normal

C1_timer_r[2]_lut_out = !C1L063 & (C1L502 & C1L75 # !C1L502 & (C1L843));
C1_timer_r[2] = DFFEAS(C1_timer_r[2]_lut_out, clk, rst_n, , , , , , );


--C1L302 is sdramCntl:sdram1|reduce_or~410
--operation mode is normal

C1L302 = C1_timer_r[5] # C1_timer_r[4] # C1_timer_r[3] # C1_timer_r[2];


--C1_timer_r[1] is sdramCntl:sdram1|timer_r[1]
--operation mode is normal

C1_timer_r[1]_lut_out = !C1L063 & (C1L502 & C1L95 # !C1L502 & (C1L643));
C1_timer_r[1] = DFFEAS(C1_timer_r[1]_lut_out, clk, rst_n, , , , , , );


--C1_timer_r[0] is sdramCntl:sdram1|timer_r[0]
--operation mode is normal

C1_timer_r[0]_lut_out = !C1L063 & (C1L502 & C1L16 # !C1L502 & (!C1_state_r.initwait));
C1_timer_r[0] = DFFEAS(C1_timer_r[0]_lut_out, clk, rst_n, , , , , , );


--C1L402 is sdramCntl:sdram1|reduce_or~411
--operation mode is normal

C1L402 = C1_timer_r[1] # C1_timer_r[0];


--C1L502 is sdramCntl:sdram1|reduce_or~412
--operation mode is normal

C1L502 = C1L102 # C1L202 # C1L302 # C1L402;


--C1L533 is sdramCntl:sdram1|status[0]~797
--operation mode is normal

C1L533 = !C1L502 & (C1L433 # !C1L02 # !C1_state_r.initwait);


--C1_done is sdramCntl:sdram1|done
--operation mode is normal

C1_done = C1_rdPipeline_r[0] # C1_wrPipeline_r[0];


--C1L143 is sdramCntl:sdram1|status~798
--operation mode is normal

C1L143 = !B1_state_r.compare & !B1_state_r.load;


--C1L992 is sdramCntl:sdram1|Select~911
--operation mode is normal

C1L992 = C1_state_r.rw & !C1_done & !C1L591 & !C1L143;


--C1_state_r.initpchg is sdramCntl:sdram1|state_r.initpchg
--operation mode is normal

C1_state_r.initpchg_lut_out = !C1_state_r.initpchg & C1L02 & C1L023 & C1L003;
C1_state_r.initpchg = DFFEAS(C1_state_r.initpchg_lut_out, clk, rst_n, , C1L523, , , , );


--C1_state_r.activate is sdramCntl:sdram1|state_r.activate
--operation mode is normal

C1_state_r.activate_lut_out = C1L992 & C1L511 & (!C1L601);
C1_state_r.activate = DFFEAS(C1_state_r.activate_lut_out, clk, rst_n, , !C1L502, , , , );


--C1L301 is sdramCntl:sdram1|cmd_x[5]~958
--operation mode is normal

C1L301 = !C1_state_r.initpchg & !C1_state_r.activate;


--C1L633 is sdramCntl:sdram1|status[1]~799
--operation mode is normal

C1L633 = !C1L502 & (C1L992 # !C1L301 # !C1L02);


--C1L243 is sdramCntl:sdram1|status~800
--operation mode is normal

C1L243 = !C1_rdPipeline_r[0] & !C1_wrPipeline_r[0] & (B1_state_r.compare # B1_state_r.load);


--C1L733 is sdramCntl:sdram1|status[2]~801
--operation mode is normal

C1L733 = C1_state_r.rw & (C1L591 # C1L243);


--C1_state_r.initsetmode is sdramCntl:sdram1|state_r.initsetmode
--operation mode is normal

C1_state_r.initsetmode_lut_out = C1_state_r.initrfsh;
C1_state_r.initsetmode = DFFEAS(C1_state_r.initsetmode_lut_out, clk, rst_n, , C1L523, , , , );


--C1_state_r.selfrefresh is sdramCntl:sdram1|state_r.selfrefresh
--operation mode is normal

C1_state_r.selfrefresh_lut_out = C1L623 & (C1_state_r.selfrefresh # C1L091 & C1L511);
C1_state_r.selfrefresh = DFFEAS(C1_state_r.selfrefresh_lut_out, clk, rst_n, , !C1L502, , , , );


--C1L833 is sdramCntl:sdram1|status[2]~802
--operation mode is normal

C1L833 = !C1L502 & (C1L733 # C1_state_r.initsetmode # C1_state_r.selfrefresh);


--C1L933 is sdramCntl:sdram1|status[3]~803
--operation mode is normal

C1L933 = C1_state_r.refreshrow # C1_state_r.activate # C1_state_r.selfrefresh;


--C1L091 is sdramCntl:sdram1|rdPipeline_x[4]~17
--operation mode is normal

C1L091 = C1_state_r.rw & (!C1L591);


--C1L043 is sdramCntl:sdram1|status[3]~804
--operation mode is normal

C1L043 = !C1L502 & (C1L933 # C1L091 & !C1L243);


--C1_cke is sdramCntl:sdram1|cke
--operation mode is normal

C1_cke_lut_out = C1L78;
C1_cke = DFFEAS(C1_cke_lut_out, clk, rst_n, , , , , , );


--C1_cmd_r[6] is sdramCntl:sdram1|cmd_r[6]
--operation mode is normal

C1_cmd_r[6]_lut_out = !C1L423 & C1L401 & (!C1L723 # !C1_state_r.rw);
C1_cmd_r[6] = DFFEAS(C1_cmd_r[6]_lut_out, clk, rst_n, , , , , , );


--C1_cmd_r[5] is sdramCntl:sdram1|cmd_r[5]
--operation mode is normal

C1_cmd_r[5]_lut_out = !C1L501 & C1L301 & C1L28 & C1L103;
C1_cmd_r[5] = DFFEAS(C1_cmd_r[5]_lut_out, clk, rst_n, , , , , , );


--C1_cmd_r[4] is sdramCntl:sdram1|cmd_r[4]
--operation mode is normal

C1_cmd_r[4]_lut_out = !C1L502 & !C1L99 & !C1L001 & !C1L201;
C1_cmd_r[4] = DFFEAS(C1_cmd_r[4]_lut_out, clk, rst_n, , , , , , );


--C1_ba_r[0] is sdramCntl:sdram1|ba_r[0]
--operation mode is normal

C1_ba_r[0]_lut_out = B1_addr_r[20];
C1_ba_r[0] = DFFEAS(C1_ba_r[0]_lut_out, clk, rst_n, , , , , , );


--C1_ba_r[1] is sdramCntl:sdram1|ba_r[1]
--operation mode is normal

C1_ba_r[1]_lut_out = B1_addr_r[21];
C1_ba_r[1] = DFFEAS(C1_ba_r[1]_lut_out, clk, rst_n, , , , , , );


--C1_sAddr_r[0] is sdramCntl:sdram1|sAddr_r[0]
--operation mode is normal

C1_sAddr_r[0]_lut_out = C1_state_r.activate & (B1_addr_r[8]) # !C1_state_r.activate & C1L303;
C1_sAddr_r[0] = DFFEAS(C1_sAddr_r[0]_lut_out, clk, rst_n, , , B1_addr_r[0], , , C1L502);


--C1_sAddr_r[1] is sdramCntl:sdram1|sAddr_r[1]
--operation mode is normal

C1_sAddr_r[1]_lut_out = C1_state_r.activate & (B1_addr_r[9]) # !C1_state_r.activate & C1L403;
C1_sAddr_r[1] = DFFEAS(C1_sAddr_r[1]_lut_out, clk, rst_n, , , B1_addr_r[1], , , C1L502);


--C1_sAddr_r[2] is sdramCntl:sdram1|sAddr_r[2]
--operation mode is normal

C1_sAddr_r[2]_lut_out = C1_state_r.activate & (B1_addr_r[10]) # !C1_state_r.activate & C1L503;
C1_sAddr_r[2] = DFFEAS(C1_sAddr_r[2]_lut_out, clk, rst_n, , , B1_addr_r[2], , , C1L502);


--C1_sAddr_r[3] is sdramCntl:sdram1|sAddr_r[3]
--operation mode is normal

C1_sAddr_r[3]_lut_out = C1_state_r.activate & (B1_addr_r[11]) # !C1_state_r.activate & C1L603;
C1_sAddr_r[3] = DFFEAS(C1_sAddr_r[3]_lut_out, clk, rst_n, , , B1_addr_r[3], , , C1L502);


--C1_sAddr_r[4] is sdramCntl:sdram1|sAddr_r[4]
--operation mode is normal

C1_sAddr_r[4]_lut_out = C1L752 & B1_addr_r[4] # !C1L752 & (B1_addr_r[12] # !C1_state_r.activate);
C1_sAddr_r[4] = DFFEAS(C1_sAddr_r[4]_lut_out, clk, rst_n, , , , , , );


--C1_sAddr_r[5] is sdramCntl:sdram1|sAddr_r[5]
--operation mode is normal

C1_sAddr_r[5]_lut_out = C1L752 & B1_addr_r[5] # !C1L752 & (B1_addr_r[13] # !C1_state_r.activate);
C1_sAddr_r[5] = DFFEAS(C1_sAddr_r[5]_lut_out, clk, rst_n, , , , , , );


--C1_sAddr_r[6] is sdramCntl:sdram1|sAddr_r[6]
--operation mode is normal

C1_sAddr_r[6]_lut_out = C1_state_r.activate & (B1_addr_r[14]) # !C1_state_r.activate & C1L703;
C1_sAddr_r[6] = DFFEAS(C1_sAddr_r[6]_lut_out, clk, rst_n, , , B1_addr_r[6], , , C1L502);


--C1_sAddr_r[7] is sdramCntl:sdram1|sAddr_r[7]
--operation mode is normal

C1_sAddr_r[7]_lut_out = C1_state_r.activate & (B1_addr_r[15]) # !C1_state_r.activate & C1L803;
C1_sAddr_r[7] = DFFEAS(C1_sAddr_r[7]_lut_out, clk, rst_n, , , B1_addr_r[7], , , C1L502);


--C1_sAddr_r[8] is sdramCntl:sdram1|sAddr_r[8]
--operation mode is normal

C1_sAddr_r[8]_lut_out = B1_addr_r[16] & C1_state_r.activate & !C1L602 & !C1L702;
C1_sAddr_r[8] = DFFEAS(C1_sAddr_r[8]_lut_out, clk, rst_n, , , , , , );


--C1_sAddr_r[9] is sdramCntl:sdram1|sAddr_r[9]
--operation mode is normal

C1_sAddr_r[9]_lut_out = B1_addr_r[17] & C1_state_r.activate & !C1L602 & !C1L702;
C1_sAddr_r[9] = DFFEAS(C1_sAddr_r[9]_lut_out, clk, rst_n, , , , , , );


--C1_sAddr_r[10] is sdramCntl:sdram1|sAddr_r[10]
--operation mode is normal

C1_sAddr_r[10]_lut_out = !C1L502 & (C1L462 # C1L203 & C1L562);
C1_sAddr_r[10] = DFFEAS(C1_sAddr_r[10]_lut_out, clk, rst_n, , , , , , );


--C1_sAddr_r[11] is sdramCntl:sdram1|sAddr_r[11]
--operation mode is normal

C1_sAddr_r[11]_lut_out = B1_addr_r[19] & C1_state_r.activate & !C1L602 & !C1L702;
C1_sAddr_r[11] = DFFEAS(C1_sAddr_r[11]_lut_out, clk, rst_n, , , , , , );


--C1_cmd_r[3] is sdramCntl:sdram1|cmd_r[3]
--operation mode is normal

C1_cmd_r[3]_lut_out = C1L49 # C1L59 # C1_state_r.initrfsh & !C1L502;
C1_cmd_r[3] = DFFEAS(C1_cmd_r[3]_lut_out, clk, rst_n, , , , , , );


--B1_err is memTest:memt|err
--operation mode is normal

B1_err_lut_out = B1L15 # B1_state_r.compare & C1_done & B1L38;
B1_err = DFFEAS(B1_err_lut_out, clk, VCC, , rst_n, , , , );


--C1L713 is sdramCntl:sdram1|state_r.rw~138
--operation mode is normal

C1L713 = C1_state_r.refreshrow # C1_state_r.activate # C1_state_r.initsetmode # C1_state_r.selfrefresh;


--B1_addr_r[17] is memTest:memt|addr_r[17]
--operation mode is arithmetic

B1_addr_r[17]_carry_eqn = B1L73;
B1_addr_r[17]_lut_out = B1_addr_r[17] $ (B1_addr_r[17]_carry_eqn);
B1_addr_r[17] = DFFEAS(B1_addr_r[17]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L93 is memTest:memt|addr_r[17]~321
--operation mode is arithmetic

B1L93 = CARRY(!B1L73 # !B1_addr_r[17]);


--B1_addr_r[11] is memTest:memt|addr_r[11]
--operation mode is arithmetic

B1_addr_r[11]_carry_eqn = B1L52;
B1_addr_r[11]_lut_out = B1_addr_r[11] $ (B1_addr_r[11]_carry_eqn);
B1_addr_r[11] = DFFEAS(B1_addr_r[11]_lut_out, clk, VCC, , B1L12, , , B1L41, );

--B1L72 is memTest:memt|addr_r[11]~325
--operation mode is arithmetic

B1L72 = CARRY(!B1L52 # !B1_addr_r[11]);


--C1_activeRow_r[0][3] is sdramCntl:sdram1|activeRow_r[0][3]
--operation mode is normal

C1_activeRow_r[0][3]_lut_out = B1_addr_r[11];
C1_activeRow_r[0][3] = DFFEAS(C1_activeRow_r[0][3]_lut_out, clk, VCC, , C1L8, , , , );


--C1_activeRow_r[0][9] is sdramCntl:sdram1|activeRow_r[0][9]
--operation mode is normal

C1_activeRow_r[0][9]_lut_out = B1_addr_r[17];
C1_activeRow_r[0][9] = DFFEAS(C1_activeRow_r[0][9]_lut_out, clk, VCC, , C1L8, , , , );


--C1L701 is sdramCntl:sdram1|combinatorial~153