bulksrc.c

Slave mode FX2LP Firmware for raw-data transfer from an external master (altera FPGA)

#pragma NOIV // Do not generate interrupt vectors
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init( void )
{ // Called once at startup
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48 MHz operation
SYNCDELAY;
REVCTL=0x02;
IFCONFIG = 0xCB;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// x MHz=1 , 48 MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48 MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , master samples asynchronous
// GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=11, FX2 in slave FIFO mode
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x84; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x86; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x88; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
PINFLAGSAB = 0xEF; // FLAGA - fixed EP8FF, FLAGB - fixed EP6FF
SYNCDELAY;
PINFLAGSCD = 0x98; // FLAGC - fixed EP2EF, FLAGD - fixed EP4EF
SYNCDELAY;
PORTACFG |= 0x80; // FLAGD, set alt. func. of PA7 pin
SYNCDELAY;
FIFOPINPOLAR = 0x00; // all signals active low
SYNCDELAY;
EP2CFG = 0xA0;
SYNCDELAY;
EP6CFG = 0xE0;
// EP4 and EP8 are not used in this implementation
SYNCDELAY; //
EP4CFG = 0x20; // clear valid bit
SYNCDELAY; //
EP8CFG = 0x60; // clear valid bit
// handle the case where we were already in AUTO mode
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
SYNCDELAY;
SYNCDELAY; //
EP2BCL = 0x00; // arm first buffer
SYNCDELAY; //
EP2BCL = 0x00; // arm second buffer
SYNCDELAY; //
EP2BCL = 0x00; // arm third buffer
SYNCDELAY; //
EP2BCL = 0x00; // arm fourth buffer
SYNCDELAY; //
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0
SYNCDELAY;
EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
SYNCDELAY;
}
void TD_Poll( void )
{ // Called repeatedly while the device is idle
// nothing to do;slave fifo's are in AUTO mode
}
BOOL TD_Suspend( void )
{ // Called before the device goes into suspend mode
return( TRUE );
}
BOOL TD_Resume( void )
{ // Called after the device resumes
return( TRUE );
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor( void )
{
return( TRUE );
}
BOOL DR_SetConfiguration( void )
{ // Called when a Set Configuration command is received
if( EZUSB_HIGHSPEED( ) )
{ // FX2LP in high speed mode
EP6AUTOINLENH = 0x02;
SYNCDELAY;
// set core AUTO commit len = 512 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
}
else
{ // FX2LP in full speed mode
EP6AUTOINLENH = 0x00;
SYNCDELAY;
// set core AUTO commit len = 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
}
Configuration = SETUPDAT[ 2 ];
return( TRUE ); // Handled by user code
}
BOOL DR_GetConfiguration( void )
{ // Called when a Get Configuration command is received
EP0BUF[ 0 ] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface( void )
{ // Called when a Set Interface command is received
AlternateSetting = SETUPDAT[ 2 ];
return( TRUE ); // Handled by user code
}
BOOL DR_GetInterface( void )
{ // Called when a Set Interface command is received
EP0BUF[ 0 ] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return( TRUE ); // Handled by user code
}
BOOL DR_GetStatus( void )
{
return( TRUE );
}
BOOL DR_ClearFeature( void )
{
return( TRUE );
}
BOOL DR_SetFeature( void )
{
return( TRUE );
}
BOOL DR_VendorCmnd( void )
{
return( TRUE );
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR( );
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp( void ) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUSP;
}
void ISR_Highspeed( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR( );
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{}
void ISR_Stub( void ) interrupt 0
{}
void ISR_Ep0in( void ) interrupt 0
{}
void ISR_Ep0out( void ) interrupt 0
{}
void ISR_Ep1in( void ) interrupt 0
{}
void ISR_Ep1out( void ) interrupt 0
{}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{}
void ISR_Ep6inout( void ) interrupt 0
{}
void ISR_Ep8inout( void ) interrupt 0
{}
void ISR_Ibn( void ) interrupt 0
{}
void ISR_Ep0pingnak( void ) interrupt 0
{}
void ISR_Ep1pingnak( void ) interrupt 0
{}
void ISR_Ep2pingnak( void ) interrupt 0
{}
void ISR_Ep4pingnak( void ) interrupt 0
{}
void ISR_Ep6pingnak( void ) interrupt 0
{}
void ISR_Ep8pingnak( void ) interrupt 0
{}
void ISR_Errorlimit( void ) interrupt 0
{}
void ISR_Ep2piderror( void ) interrupt 0
{}
void ISR_Ep4piderror( void ) interrupt 0
{}
void ISR_Ep6piderror( void ) interrupt 0
{}
void ISR_Ep8piderror( void ) interrupt 0
{}
void ISR_Ep2pflag( void ) interrupt 0
{}
void ISR_Ep4pflag( void ) interrupt 0
{}
void ISR_Ep6pflag( void ) interrupt 0
{}
void ISR_Ep8pflag( void ) interrupt 0
{}
void ISR_Ep2eflag( void ) interrupt 0
{}
void ISR_Ep4eflag( void ) interrupt 0
{}
void ISR_Ep6eflag( void ) interrupt 0
{}
void ISR_Ep8eflag( void ) interrupt 0
{}
void ISR_Ep2fflag( void ) interrupt 0
{}
void ISR_Ep4fflag( void ) interrupt 0
{}
void ISR_Ep6fflag( void ) interrupt 0
{}
void ISR_Ep8fflag( void ) interrupt 0
{}
void ISR_GpifComplete( void ) interrupt 0
{}
void ISR_GpifWaveform( void ) interrupt 0
{}