📄 bulksrc.lst
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C51 COMPILER V7.20 BULKSRC 04/13/2009 09:29:53 PAGE 1
C51 COMPILER V7.20, COMPILATION OF MODULE BULKSRC
OBJECT MODULE PLACED IN bulksrc.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE bulksrc.c DEBUG OBJECTEXTEND
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 #include "fx2.h"
3 #include "fx2regs.h"
4 #include "fx2sdly.h" // SYNCDELAY macro
5 extern BOOL GotSUD; // Received setup data flag
6 extern BOOL Sleep;
7 extern BOOL Rwuen;
8 extern BOOL Selfpwr;
9 BYTE Configuration; // Current configuration
10 BYTE AlternateSetting; // Alternate settings
11 //-----------------------------------------------------------------------------
12 // Task Dispatcher hooks
13 // The following hooks are called by the task dispatcher.
14 //-----------------------------------------------------------------------------
15 void TD_Init( void )
16 { // Called once at startup
17 1 CPUCS = 0x10; // CLKSPD[1:0]=10, for 48 MHz operation
18 1 SYNCDELAY;
19 1 REVCTL=0x02;
20 1 IFCONFIG = 0xCB;
21 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
22 1 // x MHz=1 , 48 MHz internal clk rate
23 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48 MHz
24 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
25 1 // ASYNC=1 , master samples asynchronous
26 1 // GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
27 1 // IFCFG[1:0]=11, FX2 in slave FIFO mode
28 1 // Registers which require a synchronization delay, see section 15.14
29 1 // FIFORESET FIFOPINPOLAR
30 1 // INPKTEND OUTPKTEND
31 1 // EPxBCH:L REVCTL
32 1 // GPIFTCB3 GPIFTCB2
33 1 // GPIFTCB1 GPIFTCB0
34 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
35 1 // EPxFIFOCFG EPxGPIFFLGSEL
36 1 // PINFLAGSxx EPxFIFOIRQ
37 1 // EPxFIFOIE GPIFIRQ
38 1 // GPIFIE GPIFADRH:L
39 1 // UDMACRCH:L EPxGPIFTRIG
40 1 // GPIFTRIG
41 1 SYNCDELAY;
42 1 FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
43 1 SYNCDELAY; // see TRM section 15.14
44 1 FIFORESET = 0x82; // reset, FIFO 2
45 1 SYNCDELAY; //
46 1 FIFORESET = 0x84; // reset, FIFO 4
47 1 SYNCDELAY; //
48 1 FIFORESET = 0x86; // reset, FIFO 6
49 1 SYNCDELAY; //
50 1 FIFORESET = 0x88; // reset, FIFO 8
51 1 SYNCDELAY; //
52 1 FIFORESET = 0x00; // deactivate NAK-ALL
53 1 SYNCDELAY;
54 1 PINFLAGSAB = 0xEF; // FLAGA - fixed EP8FF, FLAGB - fixed EP6FF
55 1 SYNCDELAY;
C51 COMPILER V7.20 BULKSRC 04/13/2009 09:29:53 PAGE 2
56 1 PINFLAGSCD = 0x98; // FLAGC - fixed EP2EF, FLAGD - fixed EP4EF
57 1 SYNCDELAY;
58 1 PORTACFG |= 0x80; // FLAGD, set alt. func. of PA7 pin
59 1 SYNCDELAY;
60 1 FIFOPINPOLAR = 0x00; // all signals active low
61 1 SYNCDELAY;
62 1 EP2CFG = 0xA0;
63 1 SYNCDELAY;
64 1 EP6CFG = 0xE0;
65 1 // EP4 and EP8 are not used in this implementation
66 1 SYNCDELAY; //
67 1 EP4CFG = 0x20; // clear valid bit
68 1 SYNCDELAY; //
69 1 EP8CFG = 0x60; // clear valid bit
70 1 // handle the case where we were already in AUTO mode
71 1 EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
72 1 SYNCDELAY;
73 1 SYNCDELAY; //
74 1 EP2BCL = 0x00; // arm first buffer
75 1 SYNCDELAY; //
76 1 EP2BCL = 0x00; // arm second buffer
77 1 SYNCDELAY; //
78 1 EP2BCL = 0x00; // arm third buffer
79 1 SYNCDELAY; //
80 1 EP2BCL = 0x00; // arm fourth buffer
81 1 SYNCDELAY; //
82 1 SYNCDELAY;
83 1 OUTPKTEND = 0x02;
84 1 SYNCDELAY;
85 1 OUTPKTEND = 0x02;
86 1 SYNCDELAY;
87 1 OUTPKTEND = 0x02;
88 1 SYNCDELAY;
89 1 OUTPKTEND = 0x02;
90 1 SYNCDELAY;
91 1 EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0
92 1 SYNCDELAY;
93 1 EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
94 1 SYNCDELAY;
95 1 }
96 void TD_Poll( void )
97 { // Called repeatedly while the device is idle
98 1 // nothing to do;slave fifo's are in AUTO mode
99 1 }
100 BOOL TD_Suspend( void )
101 { // Called before the device goes into suspend mode
102 1 return( TRUE );
103 1 }
104 BOOL TD_Resume( void )
105 { // Called after the device resumes
106 1 return( TRUE );
107 1 }
108 //-----------------------------------------------------------------------------
109 // Device Request hooks
110 // The following hooks are called by the end point 0 device request parser.
111 //-----------------------------------------------------------------------------
112 BOOL DR_GetDescriptor( void )
113 {
114 1 return( TRUE );
115 1 }
116 BOOL DR_SetConfiguration( void )
117 { // Called when a Set Configuration command is received
C51 COMPILER V7.20 BULKSRC 04/13/2009 09:29:53 PAGE 3
118 1 if( EZUSB_HIGHSPEED( ) )
119 1 { // FX2LP in high speed mode
120 2 EP6AUTOINLENH = 0x02;
121 2 SYNCDELAY;
122 2 // set core AUTO commit len = 512 bytes
123 2 SYNCDELAY;
124 2 EP6AUTOINLENL = 0x00;
125 2 SYNCDELAY;
126 2 }
127 1 else
128 1 { // FX2LP in full speed mode
129 2 EP6AUTOINLENH = 0x00;
130 2 SYNCDELAY;
131 2 // set core AUTO commit len = 64 bytes
132 2 SYNCDELAY;
133 2 EP6AUTOINLENL = 0x40;
134 2 SYNCDELAY;
135 2 }
136 1 Configuration = SETUPDAT[ 2 ];
137 1 return( TRUE ); // Handled by user code
138 1 }
139 BOOL DR_GetConfiguration( void )
140 { // Called when a Get Configuration command is received
141 1 EP0BUF[ 0 ] = Configuration;
142 1 EP0BCH = 0;
143 1 EP0BCL = 1;
144 1 return(TRUE); // Handled by user code
145 1 }
146 BOOL DR_SetInterface( void )
147 { // Called when a Set Interface command is received
148 1 AlternateSetting = SETUPDAT[ 2 ];
149 1 return( TRUE ); // Handled by user code
150 1 }
151 BOOL DR_GetInterface( void )
152 { // Called when a Set Interface command is received
153 1 EP0BUF[ 0 ] = AlternateSetting;
154 1 EP0BCH = 0;
155 1 EP0BCL = 1;
156 1 return( TRUE ); // Handled by user code
157 1 }
158 BOOL DR_GetStatus( void )
159 {
160 1 return( TRUE );
161 1 }
162 BOOL DR_ClearFeature( void )
163 {
164 1 return( TRUE );
165 1 }
166 BOOL DR_SetFeature( void )
167 {
168 1 return( TRUE );
169 1 }
170 BOOL DR_VendorCmnd( void )
171 {
172 1 return( TRUE );
173 1 }
174 //-----------------------------------------------------------------------------
175 // USB Interrupt Handlers
176 // The following functions are called by the USB interrupt jump table.
177 //-----------------------------------------------------------------------------
178 // Setup Data Available Interrupt Handler
179 void ISR_Sudav( void ) interrupt 0
C51 COMPILER V7.20 BULKSRC 04/13/2009 09:29:53 PAGE 4
180 {
181 1 GotSUD = TRUE; // Set flag
182 1 EZUSB_IRQ_CLEAR( );
183 1 USBIRQ = bmSUDAV; // Clear SUDAV IRQ
184 1 }
185 // Setup Token Interrupt Handler
186 void ISR_Sutok( void ) interrupt 0
187 {
188 1 EZUSB_IRQ_CLEAR( );
189 1 USBIRQ = bmSUTOK; // Clear SUTOK IRQ
190 1 }
191 void ISR_Sof( void ) interrupt 0
192 {
193 1 EZUSB_IRQ_CLEAR( );
194 1 USBIRQ = bmSOF; // Clear SOF IRQ
195 1 }
196 void ISR_Ures( void ) interrupt 0
197 {
198 1 if ( EZUSB_HIGHSPEED( ) )
199 1 {
200 2 pConfigDscr = pHighSpeedConfigDscr;
201 2 pOtherConfigDscr = pFullSpeedConfigDscr;
202 2 }
203 1 else
204 1 {
205 2 pConfigDscr = pFullSpeedConfigDscr;
206 2 pOtherConfigDscr = pHighSpeedConfigDscr;
207 2 }
208 1 EZUSB_IRQ_CLEAR( );
209 1 USBIRQ = bmURES; // Clear URES IRQ
210 1 }
211 void ISR_Susp( void ) interrupt 0
212 {
213 1 Sleep = TRUE;
214 1 EZUSB_IRQ_CLEAR( );
215 1 USBIRQ = bmSUSP;
216 1 }
217 void ISR_Highspeed( void ) interrupt 0
218 {
219 1 if ( EZUSB_HIGHSPEED( ) )
220 1 {
221 2 pConfigDscr = pHighSpeedConfigDscr;
222 2 pOtherConfigDscr = pFullSpeedConfigDscr;
223 2 }
224 1 else
225 1 {
226 2 pConfigDscr = pFullSpeedConfigDscr;
227 2 pOtherConfigDscr = pHighSpeedConfigDscr;
228 2 }
229 1 EZUSB_IRQ_CLEAR( );
230 1 USBIRQ = bmHSGRANT;
231 1 }
232 void ISR_Ep0ack( void ) interrupt 0
233 {}
234 void ISR_Stub( void ) interrupt 0
235 {}
236 void ISR_Ep0in( void ) interrupt 0
237 {}
238 void ISR_Ep0out( void ) interrupt 0
239 {}
240 void ISR_Ep1in( void ) interrupt 0
241 {}
C51 COMPILER V7.20 BULKSRC 04/13/2009 09:29:53 PAGE 5
242 void ISR_Ep1out( void ) interrupt 0
243 {}
244 void ISR_Ep2inout( void ) interrupt 0
245 {
246 1 }
247 void ISR_Ep4inout( void ) interrupt 0
248 {}
249 void ISR_Ep6inout( void ) interrupt 0
250 {}
251 void ISR_Ep8inout( void ) interrupt 0
252 {}
253 void ISR_Ibn( void ) interrupt 0
254 {}
255 void ISR_Ep0pingnak( void ) interrupt 0
256 {}
257 void ISR_Ep1pingnak( void ) interrupt 0
258 {}
259 void ISR_Ep2pingnak( void ) interrupt 0
260 {}
261 void ISR_Ep4pingnak( void ) interrupt 0
262 {}
263 void ISR_Ep6pingnak( void ) interrupt 0
264 {}
265 void ISR_Ep8pingnak( void ) interrupt 0
266 {}
267 void ISR_Errorlimit( void ) interrupt 0
268 {}
269 void ISR_Ep2piderror( void ) interrupt 0
270 {}
271 void ISR_Ep4piderror( void ) interrupt 0
272 {}
273 void ISR_Ep6piderror( void ) interrupt 0
274 {}
275 void ISR_Ep8piderror( void ) interrupt 0
276 {}
277 void ISR_Ep2pflag( void ) interrupt 0
278 {}
279 void ISR_Ep4pflag( void ) interrupt 0
280 {}
281 void ISR_Ep6pflag( void ) interrupt 0
282 {}
283 void ISR_Ep8pflag( void ) interrupt 0
284 {}
285 void ISR_Ep2eflag( void ) interrupt 0
286 {}
287 void ISR_Ep4eflag( void ) interrupt 0
288 {}
289 void ISR_Ep6eflag( void ) interrupt 0
290 {}
291 void ISR_Ep8eflag( void ) interrupt 0
292 {}
293 void ISR_Ep2fflag( void ) interrupt 0
294 {}
295 void ISR_Ep4fflag( void ) interrupt 0
296 {}
297 void ISR_Ep6fflag( void ) interrupt 0
298 {}
299 void ISR_Ep8fflag( void ) interrupt 0
300 {}
301 void ISR_GpifComplete( void ) interrupt 0
302 {}
303 void ISR_GpifWaveform( void ) interrupt 0
C51 COMPILER V7.20 BULKSRC 04/13/2009 09:29:53 PAGE 6
304 {}
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 554 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 2 ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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