📄 sd_rfrsh.rpt
字号:
- 11 B 01 TFFE + t 0 0 0 1 10 0 5 rfrsh_cntr10 (:10)
- 10 B 01 TFFE + t 0 0 0 1 9 0 6 rfrsh_cntr9 (:11)
- 8 B 01 TFFE + t 0 0 0 1 8 0 7 rfrsh_cntr8 (:12)
- 7 B 01 TFFE + t 0 0 0 1 7 0 8 rfrsh_cntr7 (:13)
- 6 B 01 TFFE + t 0 0 0 1 6 0 9 rfrsh_cntr6 (:14)
- 5 B 01 TFFE + t 0 0 0 1 5 0 10 rfrsh_cntr5 (:15)
- 4 B 01 TFFE + t 0 0 0 1 10 0 10 rfrsh_cntr4 (:16)
- 3 B 01 TFFE + t 0 0 0 1 10 0 10 rfrsh_cntr3 (:17)
- 2 B 01 DFFE + t 1 0 0 1 10 0 10 rfrsh_cntr2 (:18)
- 1 B 01 DFFE + t 0 0 0 1 10 0 10 rfrsh_cntr1 (:19)
- 12 B 01 DFFE + t 0 0 0 1 0 0 11 rfrsh_cntr0 (:20)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\sdram_vhdl_lattice\sd_rfrsh.rpt
sd_rfrsh
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
FastTrack
Row Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
02: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
03: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
04: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
05: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Device-Specific Information: d:\sdram_vhdl_lattice\sd_rfrsh.rpt
sd_rfrsh
** EQUATIONS **
clk : INPUT;
rst_l : INPUT;
sdram_cycle3 : INPUT;
sdram_setup : INPUT;
-- Node name is ':20' = 'rfrsh_cntr0'
-- Equation name is 'rfrsh_cntr0', location is LC12_B1, type is buried.
rfrsh_cntr0 = DFFE( _EQ001 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ001 = !rfrsh_cntr0 & sdram_setup;
-- Node name is ':19' = 'rfrsh_cntr1'
-- Equation name is 'rfrsh_cntr1', location is LC1_B1, type is buried.
rfrsh_cntr1 = DFFE( _EQ002 $ VCC, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ002 = rfrsh_cntr0 & rfrsh_cntr1
# !rfrsh_cntr0 & !rfrsh_cntr1
# rfrsh_cntr0 & rfrsh_cntr2 & rfrsh_cntr3 & rfrsh_cntr4 &
!rfrsh_cntr5 & !rfrsh_cntr6 & !rfrsh_cntr7 & !rfrsh_cntr8 &
!rfrsh_cntr9 & rfrsh_cntr10
# !sdram_setup;
-- Node name is ':18' = 'rfrsh_cntr2'
-- Equation name is 'rfrsh_cntr2', location is LC2_B1, type is buried.
rfrsh_cntr2 = DFFE( _EQ003 $ _EQ004, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ003 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & sdram_setup & _X001
# !rfrsh_cntr1 & !rfrsh_cntr2 & sdram_setup & _X001
# !rfrsh_cntr0 & !rfrsh_cntr2 & sdram_setup & _X001;
_X001 = EXP( rfrsh_cntr0 & !rfrsh_cntr1 & rfrsh_cntr3 & rfrsh_cntr4 &
!rfrsh_cntr5 & !rfrsh_cntr6 & !rfrsh_cntr7 & !rfrsh_cntr8 &
!rfrsh_cntr9 & rfrsh_cntr10);
_EQ004 = sdram_setup & _X001;
_X001 = EXP( rfrsh_cntr0 & !rfrsh_cntr1 & rfrsh_cntr3 & rfrsh_cntr4 &
!rfrsh_cntr5 & !rfrsh_cntr6 & !rfrsh_cntr7 & !rfrsh_cntr8 &
!rfrsh_cntr9 & rfrsh_cntr10);
-- Node name is ':17' = 'rfrsh_cntr3'
-- Equation name is 'rfrsh_cntr3', location is LC3_B1, type is buried.
rfrsh_cntr3 = TFFE( _EQ005, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ005 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & sdram_setup
# rfrsh_cntr0 & rfrsh_cntr2 & rfrsh_cntr3 & rfrsh_cntr4 &
!rfrsh_cntr5 & !rfrsh_cntr6 & !rfrsh_cntr7 & !rfrsh_cntr8 &
!rfrsh_cntr9 & rfrsh_cntr10
# rfrsh_cntr3 & !sdram_setup;
-- Node name is ':16' = 'rfrsh_cntr4'
-- Equation name is 'rfrsh_cntr4', location is LC4_B1, type is buried.
rfrsh_cntr4 = TFFE( _EQ006, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ006 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
sdram_setup
# rfrsh_cntr0 & rfrsh_cntr2 & rfrsh_cntr3 & rfrsh_cntr4 &
!rfrsh_cntr5 & !rfrsh_cntr6 & !rfrsh_cntr7 & !rfrsh_cntr8 &
!rfrsh_cntr9 & rfrsh_cntr10
# rfrsh_cntr4 & !sdram_setup;
-- Node name is ':15' = 'rfrsh_cntr5'
-- Equation name is 'rfrsh_cntr5', location is LC5_B1, type is buried.
rfrsh_cntr5 = TFFE( _EQ007, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ007 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & sdram_setup
# rfrsh_cntr5 & !sdram_setup;
-- Node name is ':14' = 'rfrsh_cntr6'
-- Equation name is 'rfrsh_cntr6', location is LC6_B1, type is buried.
rfrsh_cntr6 = TFFE( _EQ008, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ008 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & sdram_setup
# rfrsh_cntr6 & !sdram_setup;
-- Node name is ':13' = 'rfrsh_cntr7'
-- Equation name is 'rfrsh_cntr7', location is LC7_B1, type is buried.
rfrsh_cntr7 = TFFE( _EQ009, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ009 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6 & sdram_setup
# rfrsh_cntr7 & !sdram_setup;
-- Node name is ':12' = 'rfrsh_cntr8'
-- Equation name is 'rfrsh_cntr8', location is LC8_B1, type is buried.
rfrsh_cntr8 = TFFE( _EQ010, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ010 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6 & rfrsh_cntr7 &
sdram_setup
# rfrsh_cntr8 & !sdram_setup;
-- Node name is ':11' = 'rfrsh_cntr9'
-- Equation name is 'rfrsh_cntr9', location is LC10_B1, type is buried.
rfrsh_cntr9 = TFFE( _EQ011, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ011 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6 & rfrsh_cntr7 &
rfrsh_cntr8 & sdram_setup
# rfrsh_cntr9 & !sdram_setup;
-- Node name is ':10' = 'rfrsh_cntr10'
-- Equation name is 'rfrsh_cntr10', location is LC11_B1, type is buried.
rfrsh_cntr10 = TFFE( _EQ012, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ012 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6 & rfrsh_cntr7 &
rfrsh_cntr8 & rfrsh_cntr9 & sdram_setup
# rfrsh_cntr0 & !rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & !rfrsh_cntr5 & !rfrsh_cntr6 & !rfrsh_cntr7 &
!rfrsh_cntr8 & !rfrsh_cntr9 & rfrsh_cntr10
# rfrsh_cntr10 & !sdram_setup;
-- Node name is 'rfrsh_req'
-- Equation name is 'rfrsh_req', type is output
rfrsh_req = _LC9_B1;
-- Node name is ':8'
-- Equation name is '_LC9_B1', type is buried
_LC9_B1 = DFFE( _EQ013 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ013 = rfrsh_cntr0 & !rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & !rfrsh_cntr5 & !rfrsh_cntr6 & !rfrsh_cntr7 &
!rfrsh_cntr8 & !rfrsh_cntr9 & rfrsh_cntr10
# _LC9_B1 & !sdram_cycle3;
Project Information d:\sdram_vhdl_lattice\sd_rfrsh.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX9000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 7,555K
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