📄 sd_state.rpt
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** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
IOC LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 4 B 01 DFFE + t 1 0 0 4 7 1 3 sdram_cycle_sig3 (:14)
- 9 B 01 DFFE + t 0 0 0 3 3 1 3 sdram_cycle_sig2 (:15)
- 11 B 01 DFFE + t 0 0 0 2 4 1 3 sdram_cycle_sig1 (:16)
- 15 B 01 DFFE + t 4 0 0 4 7 1 7 sdram_cycle_sig0 (:17)
- 1 B 01 TFFE + t 0 0 0 1 4 1 3 state_cntr_sig3 (:18)
- 2 B 01 DFFE + t 0 0 0 1 3 1 3 state_cntr_sig2 (:19)
- 3 B 01 DFFE + t 0 0 0 1 2 1 4 state_cntr_sig1 (:20)
- 5 B 01 DFFE + t 0 0 0 1 1 1 5 state_cntr_sig0 (:21)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\sdram_vhdl_lattice\sd_state.rpt
sd_state
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
FastTrack
Row Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 7/ 96( 7%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/48( 10%) 0/20( 0%) 5/20( 25%) 0/20( 0%)
02: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
03: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
04: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
05: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Device-Specific Information: d:\sdram_vhdl_lattice\sd_state.rpt
sd_state
** EQUATIONS **
clk : INPUT;
cmnd_cycle_req : INPUT;
rfrsh_req : INPUT;
rst_l : INPUT;
sdram_cs_l : INPUT;
-- Node name is ':17' = 'sdram_cycle_sig0'
-- Equation name is 'sdram_cycle_sig0', location is LC15_B1, type is buried.
sdram_cycle_sig0 = DFFE( _EQ001 $ VCC, GLOBAL( clk), VCC, rst_l, VCC);
_EQ001 = _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!sdram_cycle_sig0 & sdram_cycle_sig1 & !sdram_cycle_sig2 &
!sdram_cycle_sig3 & state_cntr_sig3);
_X002 = EXP(!cmnd_cycle_req & !rfrsh_req & sdram_cs_l & sdram_cycle_sig0 &
!sdram_cycle_sig1 & !sdram_cycle_sig2 & !sdram_cycle_sig3);
_X003 = EXP( sdram_cs_l & !sdram_cycle_sig0 & !sdram_cycle_sig1 &
sdram_cycle_sig2 & !sdram_cycle_sig3);
_X004 = EXP(!sdram_cycle_sig0 & !sdram_cycle_sig1 & !sdram_cycle_sig2 &
sdram_cycle_sig3 & !state_cntr_sig0 & !state_cntr_sig1 &
state_cntr_sig2 & state_cntr_sig3);
-- Node name is ':16' = 'sdram_cycle_sig1'
-- Equation name is 'sdram_cycle_sig1', location is LC11_B1, type is buried.
sdram_cycle_sig1 = DFFE( _EQ002 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ002 = cmnd_cycle_req & sdram_cycle_sig0 & !sdram_cycle_sig1 &
!sdram_cycle_sig2 & !sdram_cycle_sig3
# !sdram_cycle_sig0 & sdram_cycle_sig1 & !sdram_cycle_sig2 &
!sdram_cycle_sig3 & !state_cntr_sig3;
-- Node name is ':15' = 'sdram_cycle_sig2'
-- Equation name is 'sdram_cycle_sig2', location is LC9_B1, type is buried.
sdram_cycle_sig2 = DFFE( _EQ003 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ003 = !sdram_cs_l & !sdram_cycle_sig0 & !sdram_cycle_sig1 &
sdram_cycle_sig2 & !sdram_cycle_sig3
# !cmnd_cycle_req & !sdram_cs_l & sdram_cycle_sig0 &
!sdram_cycle_sig1 & !sdram_cycle_sig2 & !sdram_cycle_sig3;
-- Node name is ':14' = 'sdram_cycle_sig3'
-- Equation name is 'sdram_cycle_sig3', location is LC4_B1, type is buried.
sdram_cycle_sig3 = DFFE( _EQ004 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ004 = !cmnd_cycle_req & rfrsh_req & sdram_cs_l & sdram_cycle_sig0 &
!sdram_cycle_sig1 & !sdram_cycle_sig2 & !sdram_cycle_sig3
# !sdram_cycle_sig0 & !sdram_cycle_sig1 & !sdram_cycle_sig2 &
sdram_cycle_sig3 & _X005;
_X005 = EXP(!state_cntr_sig0 & !state_cntr_sig1 & state_cntr_sig2 &
state_cntr_sig3);
-- Node name is 'sdram_cycle0'
-- Equation name is 'sdram_cycle0', type is output
sdram_cycle0 = sdram_cycle_sig0;
-- Node name is 'sdram_cycle1'
-- Equation name is 'sdram_cycle1', type is output
sdram_cycle1 = sdram_cycle_sig1;
-- Node name is 'sdram_cycle2'
-- Equation name is 'sdram_cycle2', type is output
sdram_cycle2 = sdram_cycle_sig2;
-- Node name is 'sdram_cycle3'
-- Equation name is 'sdram_cycle3', type is output
sdram_cycle3 = sdram_cycle_sig3;
-- Node name is ':21' = 'state_cntr_sig0'
-- Equation name is 'state_cntr_sig0', location is LC5_B1, type is buried.
state_cntr_sig0 = DFFE( _EQ005 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ005 = !sdram_cycle_sig0 & !state_cntr_sig0;
-- Node name is ':20' = 'state_cntr_sig1'
-- Equation name is 'state_cntr_sig1', location is LC3_B1, type is buried.
state_cntr_sig1 = DFFE( _EQ006 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ006 = !sdram_cycle_sig0 & state_cntr_sig0 & !state_cntr_sig1
# !sdram_cycle_sig0 & !state_cntr_sig0 & state_cntr_sig1;
-- Node name is ':19' = 'state_cntr_sig2'
-- Equation name is 'state_cntr_sig2', location is LC2_B1, type is buried.
state_cntr_sig2 = DFFE( _EQ007 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ007 = !sdram_cycle_sig0 & !state_cntr_sig0 & state_cntr_sig2
# !sdram_cycle_sig0 & !state_cntr_sig1 & state_cntr_sig2
# !sdram_cycle_sig0 & state_cntr_sig0 & state_cntr_sig1 &
!state_cntr_sig2;
-- Node name is ':18' = 'state_cntr_sig3'
-- Equation name is 'state_cntr_sig3', location is LC1_B1, type is buried.
state_cntr_sig3 = TFFE( _EQ008, GLOBAL( clk), rst_l, VCC, VCC);
_EQ008 = !sdram_cycle_sig0 & state_cntr_sig0 & state_cntr_sig1 &
state_cntr_sig2
# sdram_cycle_sig0 & state_cntr_sig3;
-- Node name is 'state_cntr0'
-- Equation name is 'state_cntr0', type is output
state_cntr0 = state_cntr_sig0;
-- Node name is 'state_cntr1'
-- Equation name is 'state_cntr1', type is output
state_cntr1 = state_cntr_sig1;
-- Node name is 'state_cntr2'
-- Equation name is 'state_cntr2', type is output
state_cntr2 = state_cntr_sig2;
-- Node name is 'state_cntr3'
-- Equation name is 'state_cntr3', type is output
state_cntr3 = state_cntr_sig3;
Project Information d:\sdram_vhdl_lattice\sd_state.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX9000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,249K
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