📄 sd_cnfg.rpt
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Row FastTrack Interconnect:
FastTrack
Row Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 6/ 96( 6%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
C: 1/ 96( 1%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 1/ 96( 1%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/48( 4%) 0/20( 0%) 2/20( 10%) 0/20( 0%)
02: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
03: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
04: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
05: 0/48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Device-Specific Information: d:\sdram_vhdl_lattice\sd_cnfg.rpt
sd_cnfg
** EQUATIONS **
clk : INPUT;
rst_l : INPUT;
sdram_cycle1 : INPUT;
sdram_en : INPUT;
state_cntr2 : INPUT;
state_cntr3 : INPUT;
-- Node name is 'cmnd_cycle_req'
-- Equation name is 'cmnd_cycle_req', type is output
cmnd_cycle_req = _LC11_B1;
-- Node name is 'sdram_cmnd0'
-- Equation name is 'sdram_cmnd0', type is output
sdram_cmnd0 = _LC2_B1;
-- Node name is 'sdram_cmnd1'
-- Equation name is 'sdram_cmnd1', type is output
sdram_cmnd1 = _LC15_B1;
-- Node name is ':32' = 'sdram_en1'
-- Equation name is 'sdram_en1', location is LC5_B1, type is buried.
sdram_en1 = DFFE( sdram_en $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
-- Node name is ':33' = 'sdram_en2'
-- Equation name is 'sdram_en2', location is LC7_B1, type is buried.
sdram_en2 = DFFE( sdram_en1 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
-- Node name is 'sdram_mode_reg0~1'
-- Equation name is 'sdram_mode_reg0~1', location is LC9_A2, type is buried.
sdram_mode_reg0~1 = LCELL( VCC $ GND);
-- Node name is 'sdram_mode_reg0'
-- Equation name is 'sdram_mode_reg0', type is output
sdram_mode_reg0 = sdram_mode_reg0~1;
-- Node name is 'sdram_mode_reg1~1'
-- Equation name is 'sdram_mode_reg1~1', location is LC9_D4, type is buried.
sdram_mode_reg1~1 = LCELL( VCC $ GND);
-- Node name is 'sdram_mode_reg1'
-- Equation name is 'sdram_mode_reg1', type is output
sdram_mode_reg1 = sdram_mode_reg1~1;
-- Node name is 'sdram_mode_reg2'
-- Equation name is 'sdram_mode_reg2', type is output
sdram_mode_reg2 = GND;
-- Node name is 'sdram_mode_reg3'
-- Equation name is 'sdram_mode_reg3', type is output
sdram_mode_reg3 = GND;
-- Node name is 'sdram_mode_reg4'
-- Equation name is 'sdram_mode_reg4', type is output
sdram_mode_reg4 = GND;
-- Node name is 'sdram_mode_reg5~1'
-- Equation name is 'sdram_mode_reg5~1', location is LC9_C3, type is buried.
sdram_mode_reg5~1 = LCELL( VCC $ GND);
-- Node name is 'sdram_mode_reg5'
-- Equation name is 'sdram_mode_reg5', type is output
sdram_mode_reg5 = sdram_mode_reg5~1;
-- Node name is 'sdram_mode_reg6'
-- Equation name is 'sdram_mode_reg6', type is output
sdram_mode_reg6 = GND;
-- Node name is 'sdram_mode_reg7'
-- Equation name is 'sdram_mode_reg7', type is output
sdram_mode_reg7 = GND;
-- Node name is 'sdram_mode_reg8'
-- Equation name is 'sdram_mode_reg8', type is output
sdram_mode_reg8 = GND;
-- Node name is 'sdram_mode_reg9'
-- Equation name is 'sdram_mode_reg9', type is output
sdram_mode_reg9 = GND;
-- Node name is 'sdram_mode_reg10'
-- Equation name is 'sdram_mode_reg10', type is output
sdram_mode_reg10 = GND;
-- Node name is 'sdram_mode_reg11'
-- Equation name is 'sdram_mode_reg11', type is output
sdram_mode_reg11 = GND;
-- Node name is 'sdram_setup'
-- Equation name is 'sdram_setup', type is output
sdram_setup = _LC1_B1;
-- Node name is ':37' = 'state0'
-- Equation name is 'state0', location is LC8_B1, type is buried.
state0 = DFFE( _EQ001 $ _EQ002, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ001 = sdram_cycle1 & state_cntr3 & state0 & !state2 & !state3 &
_X001
# sdram_cycle1 & state_cntr2 & state0 & state1 & state2 &
!state3 & _X001
# sdram_cycle1 & state_cntr3 & state0 & !state1 & !state3 &
_X001;
_X001 = EXP(!sdram_en2 & !state0 & !state1 & !state2);
_EQ002 = !state3 & _X001;
_X001 = EXP(!sdram_en2 & !state0 & !state1 & !state2);
-- Node name is ':36' = 'state1'
-- Equation name is 'state1', location is LC3_B1, type is buried.
state1 = TFFE( _EQ003, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ003 = sdram_cycle1 & state_cntr3 & state0 & !state1 & !state3
# sdram_cycle1 & state_cntr3 & state0 & state1 & !state2
# sdram_cycle1 & state_cntr2 & state0 & state1 & state2
# state1 & state3;
-- Node name is ':35' = 'state2'
-- Equation name is 'state2', location is LC6_B1, type is buried.
state2 = TFFE( _EQ004, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ004 = sdram_cycle1 & state_cntr3 & state0 & state1 & !state2 &
!state3
# sdram_cycle1 & state_cntr2 & state0 & state1 & state2
# state2 & state3;
-- Node name is ':34' = 'state3'
-- Equation name is 'state3', location is LC4_B1, type is buried.
state3 = DFFE( _EQ005 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ005 = sdram_cycle1 & state_cntr2 & state0 & state1 & state2 &
!state3
# !state0 & !state1 & !state2 & state3;
-- Node name is ':24'
-- Equation name is '_LC15_B1', type is buried
_LC15_B1 = DFFE( _EQ006 $ _EQ007, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ006 = sdram_cycle1 & state_cntr2 & state0 & state1 & state2 &
!state3 & _X002 & _X003
# !_LC15_B1 & state0 & !state3 & _X002 & _X003
# sdram_cycle1 & state_cntr3 & state0 & !state3 & _X002 & _X003 &
_X004;
_X002 = EXP( sdram_en2 & !state0 & !state1 & !state2);
_X003 = EXP(!_LC15_B1 & !state1 & !state2);
_X004 = EXP( state1 & state2);
_EQ007 = !state3 & _X002 & _X003;
_X002 = EXP( sdram_en2 & !state0 & !state1 & !state2);
_X003 = EXP(!_LC15_B1 & !state1 & !state2);
-- Node name is ':26'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( _EQ008 $ _EQ009, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ008 = !state0 & !state1 & state2 & !state3 & _X005 & _X006 & _X007
# !_LC2_B1 & state0 & !state3 & _X005 & _X006 & _X007
# sdram_cycle1 & state_cntr3 & state0 & !state3 & _X004 & _X005 &
_X006 & _X007;
_X005 = EXP( sdram_cycle1 & state_cntr2 & state0 & state1 & state2);
_X006 = EXP(!_LC2_B1 & !sdram_en2 & !state2);
_X007 = EXP(!state0 & state1 & !state2);
_X004 = EXP( state1 & state2);
_EQ009 = !state3 & _X005 & _X006 & _X007;
_X005 = EXP( sdram_cycle1 & state_cntr2 & state0 & state1 & state2);
_X006 = EXP(!_LC2_B1 & !sdram_en2 & !state2);
_X007 = EXP(!state0 & state1 & !state2);
-- Node name is ':28'
-- Equation name is '_LC11_B1', type is buried
_LC11_B1 = DFFE( _EQ010 $ _EQ011, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ010 = sdram_cycle1 & state_cntr2 & state0 & state1 & state2 &
!state3 & _X008
# !_LC11_B1 & state0 & !state3 & _X008
# sdram_cycle1 & state_cntr3 & state0 & !state3 & _X004 & _X008;
_X008 = EXP(!_LC11_B1 & !sdram_en2 & !state1 & !state2);
_X004 = EXP( state1 & state2);
_EQ011 = !state3 & _X008;
_X008 = EXP(!_LC11_B1 & !sdram_en2 & !state1 & !state2);
-- Node name is ':30'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( _EQ012 $ _EQ013, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ012 = sdram_cycle1 & state_cntr3 & state0 & _X004 & _X009 & _X010
# !state0 & _X009 & _X010 & _X011
# !_LC1_B1 & !state3 & _X009 & _X010 & _X012;
_X004 = EXP( state1 & state2);
_X009 = EXP( sdram_en2 & !state0 & !state3);
_X010 = EXP( state0 & state3);
_X011 = EXP(!state1 & !state2);
_X012 = EXP( sdram_cycle1 & state_cntr2 & state1 & state2);
_EQ013 = _X009 & _X010;
_X009 = EXP( sdram_en2 & !state0 & !state3);
_X010 = EXP( state0 & state3);
Project Information d:\sdram_vhdl_lattice\sd_cnfg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX9000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 7,783K
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