📄 sd_cnfg.rpt
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Project Information d:\sdram_vhdl_lattice\sd_cnfg.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/19/2009 21:48:24
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SD_CNFG
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
sd_cnfg EPM9320LC84-15 6 16 0 13 12 4 %
User Pins: 6 16 0
Project Information d:\sdram_vhdl_lattice\sd_cnfg.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'sdram_cycle3'
Warning: Ignored unnecessary INPUT pin 'sdram_cycle2'
Warning: Ignored unnecessary INPUT pin 'sdram_cycle0'
Warning: Ignored unnecessary INPUT pin 'state_cntr1'
Warning: Ignored unnecessary INPUT pin 'state_cntr0'
Project Information d:\sdram_vhdl_lattice\sd_cnfg.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
INFO: Signal 'rst_l' chosen for auto global Clear
Device-Specific Information: d:\sdram_vhdl_lattice\sd_cnfg.rpt
sd_cnfg
***** Logic for device 'sd_cnfg' compiled without errors.
Device: EPM9320LC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
User Code = ffff
MultiVolt I/O = OFF
s s
d t
r a
a R R R R R R R R t R R R R R R R R
m E E E E E E E E e E E E E E E E E
_ S S S S S S S S _ S S S S S S S S
c E E E E E E E E c E E E E V E E E E
m R R R R R R R R n R R R R C R R R R
n V V V V G V V V V c t V V V V C V V V V
d E E E E N E E E E l r E E E E I E E E E
0 D D D D D D D D D k 3 D D D D O D D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESERVED | 12 74 | RESERVED
rst_l | 13 73 | RESERVED
VCCINT | 14 72 | state_cntr2
VCCIO | 15 71 | VCCINT
sdram_mode_reg10 | 16 70 | GND
sdram_mode_reg1 | 17 69 | sdram_mode_reg9
GND | 18 68 | sdram_mode_reg11
sdram_mode_reg6 | 19 67 | GND
sdram_mode_reg5 | 20 66 | sdram_mode_reg7
VCCINT | 21 65 | sdram_mode_reg4
sdram_cmnd1 | 22 EPM9320LC84-15 64 | VCCINT
sdram_cycle1 | 23 63 | cmnd_cycle_req
GND | 24 62 | sdram_en
GND | 25 61 | GND
sdram_mode_reg2 | 26 60 | VCCIO
sdram_mode_reg0 | 27 59 | sdram_mode_reg3
VCCINT | 28 58 | sdram_mode_reg8
N.C. | 29 57 | VCCINT
#TDO | 30 56 | ^VPP
sdram_setup | 31 55 | #TMS
RESERVED | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R V R R R R # # R R R R G R R R R R
E E E E C E E E E T T E E E E N E E E E E
S S S S C S S S S D C S S S S D S S S S S
E E E E I E E E E I K E E E E E E E E E
R R R R O R R R R R R R R R R R R R
V V V V V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\sdram_vhdl_lattice\sd_cnfg.rpt
sd_cnfg
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External Shareable
Block Logic Cells Driven Driven Clocks Presets Interconnect Expanders
A2 1/16( 6%) 0/16( 0%) 1/16( 6%) 0/2 0/2 0/33( 0%) 0/16( 0%)
B1 10/16( 62%) 2/16( 12%) 2/16( 12%) 0/2 0/2 4/33( 12%) 12/16( 75%)
C3 1/16( 6%) 0/16( 0%) 1/16( 6%) 0/2 0/2 0/33( 0%) 0/16( 0%)
D4 1/16( 6%) 0/16( 0%) 1/16( 6%) 0/2 0/2 0/33( 0%) 0/16( 0%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 18/56 ( 32%)
Total logic cells used: 13/320 ( 4%)
Total shareable expanders used: 12/320 ( 3%)
Total Turbo logic cells used: 13/320 ( 4%)
Total shareable expanders not available (n/a): 0/320 ( 0%)
Average fan-in: 6.61
Total fan-in: 86
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total logic cells required: 13
Total flipflops required: 10
Total product terms required: 46
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Total packed registers required: 0
Synthesized logic cells: 0/ 320 ( 0%)
Logic Cell Counts
Column: 01 02 03 04 05 Total
A: 0 1 0 0 0 1
B: 10 0 0 0 0 10
C: 0 0 1 0 0 1
D: 0 0 0 1 0 1
Total: 10 1 1 1 0 13
Device-Specific Information: d:\sdram_vhdl_lattice\sd_cnfg.rpt
sd_cnfg
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
1 - - -- INPUT G 0 0 0 0 0 0 0 clk
13 - - -- INPUT G 0 0 0 0 0 0 0 rst_l
23 - B -- INPUT 0 0 0 0 0 0 8 sdram_cycle1
62 - B -- INPUT 0 0 0 0 0 0 1 sdram_en
72 - - -- INPUT 0 0 0 0 0 0 8 state_cntr2
84 - - -- INPUT 0 0 0 0 0 0 7 state_cntr3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\sdram_vhdl_lattice\sd_cnfg.rpt
sd_cnfg
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
63 - B -- OUTPUT 0 0 0 0 1 0 0 cmnd_cycle_req
11 - - 01 OUTPUT 0 0 0 0 1 0 0 sdram_cmnd0
22 - B -- OUTPUT 0 0 0 0 1 0 0 sdram_cmnd1
27 - A -- OUTPUT 0 0 0 0 1 0 0 sdram_mode_reg0
17 - D -- OUTPUT 0 0 0 0 1 0 0 sdram_mode_reg1
26 - A -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg2
59 - A -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg3
65 - C -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg4
20 - C -- OUTPUT 0 0 0 0 1 0 0 sdram_mode_reg5
19 - C -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg6
66 - C -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg7
58 - A -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg8
69 - D -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg9
16 - D -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg10
68 - D -- OUTPUT 0 0 0 0 0 0 0 sdram_mode_reg11
31 - - 01 OUTPUT 0 0 0 0 1 0 0 sdram_setup
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\sdram_vhdl_lattice\sd_cnfg.rpt
sd_cnfg
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
IOC LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 9 A 02 LCELL t 0 0 0 0 0 1 0 sdram_mode_reg0~1
- 9 D 04 LCELL t 0 0 0 0 0 1 0 sdram_mode_reg1~1
- 9 C 03 LCELL t 0 0 0 0 0 1 0 sdram_mode_reg5~1
- 15 B 01 DFFE + t 3 1 0 3 5 1 0 :24
- 2 B 01 DFFE + t 4 1 0 3 5 1 0 :26
- 11 B 01 DFFE + t 2 1 0 3 5 1 0 :28
- 1 B 01 DFFE + t 5 1 0 3 5 1 0 :30
- 5 B 01 DFFE + t 0 0 0 1 0 0 1 sdram_en1 (:32)
- 7 B 01 DFFE + t 0 0 0 0 1 0 5 sdram_en2 (:33)
- 4 B 01 DFFE + t 0 0 0 2 3 0 7 state3 (:34)
- 6 B 01 TFFE + t 0 0 0 3 3 0 7 state2 (:35)
- 3 B 01 TFFE + t 0 0 0 3 3 0 7 state1 (:36)
- 8 B 01 DFFE + t 1 0 0 3 4 0 7 state0 (:37)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\sdram_vhdl_lattice\sd_cnfg.rpt
sd_cnfg
** FASTTRACK INTERCONNECT UTILIZATION **
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