system.h

FPGA应用如sd卡控制

/* system.h
 *
 * Machine generated for a CPU named "cpu_0" as defined in:
 * D:\Test\c20_bga_pcf8563\software\c20_bga_i2c_syslib\..\..\nios.ptf
 *
 * Generated: 2007-04-25 20:15:50.531
 *
 */
#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "nios"
#define ALT_CPU_NAME "cpu_0"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONE"
#define ALTERA_NIOS_DEV_BOARD_CYCLONE_2C35
#define ALT_STDIN "/dev/null"
#define ALT_STDOUT "/dev/null"
#define ALT_STDERR "/dev/null"
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"

#define NIOS2_ICACHE_SIZE 2048
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x01000020
#define NIOS2_RESET_ADDR 0x00000000

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __OC_I2C_MASTER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __SRAM_256X32BIT
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_SPI
#define __AUDIO_DAC_FIFO
#define __ALTERA_AVALON_CFI_FLASH

/*
 * oc_i2c_master_0 configuration
 *
 */

#define OC_I2C_MASTER_0_NAME "/dev/oc_i2c_master_0"
#define OC_I2C_MASTER_0_TYPE "oc_i2c_master"
#define OC_I2C_MASTER_0_BASE 0x00900800
#define OC_I2C_MASTER_0_SPAN 32
#define OC_I2C_MASTER_0_IRQ 0

/*
 * pio_pcf8563_int configuration
 *
 */

#define PIO_PCF8563_INT_NAME "/dev/pio_pcf8563_int"
#define PIO_PCF8563_INT_TYPE "altera_avalon_pio"
#define PIO_PCF8563_INT_BASE 0x00900840
#define PIO_PCF8563_INT_SPAN 16
#define PIO_PCF8563_INT_IRQ 1
#define PIO_PCF8563_INT_DO_TEST_BENCH_WIRING 0
#define PIO_PCF8563_INT_DRIVEN_SIM_VALUE 0x0000
#define PIO_PCF8563_INT_HAS_TRI 0
#define PIO_PCF8563_INT_HAS_OUT 0
#define PIO_PCF8563_INT_HAS_IN 1
#define PIO_PCF8563_INT_CAPTURE 1
#define PIO_PCF8563_INT_EDGE_TYPE "FALLING"
#define PIO_PCF8563_INT_IRQ_TYPE "EDGE"
#define PIO_PCF8563_INT_FREQ 50000000

/*
 * pio_pcf8563_clkout configuration
 *
 */

#define PIO_PCF8563_CLKOUT_NAME "/dev/pio_pcf8563_clkout"
#define PIO_PCF8563_CLKOUT_TYPE "altera_avalon_pio"
#define PIO_PCF8563_CLKOUT_BASE 0x00900850
#define PIO_PCF8563_CLKOUT_SPAN 16
#define PIO_PCF8563_CLKOUT_DO_TEST_BENCH_WIRING 0
#define PIO_PCF8563_CLKOUT_DRIVEN_SIM_VALUE 0x0000
#define PIO_PCF8563_CLKOUT_HAS_TRI 0
#define PIO_PCF8563_CLKOUT_HAS_OUT 0
#define PIO_PCF8563_CLKOUT_HAS_IN 1
#define PIO_PCF8563_CLKOUT_CAPTURE 0
#define PIO_PCF8563_CLKOUT_EDGE_TYPE "NONE"
#define PIO_PCF8563_CLKOUT_IRQ_TYPE "NONE"
#define PIO_PCF8563_CLKOUT_FREQ 50000000

/*
 * pio_led configuration
 *
 */

#define PIO_LED_NAME "/dev/pio_led"
#define PIO_LED_TYPE "altera_avalon_pio"
#define PIO_LED_BASE 0x00900860
#define PIO_LED_SPAN 16
#define PIO_LED_DO_TEST_BENCH_WIRING 0
#define PIO_LED_DRIVEN_SIM_VALUE 0x0000
#define PIO_LED_HAS_TRI 0
#define PIO_LED_HAS_OUT 1
#define PIO_LED_HAS_IN 0
#define PIO_LED_CAPTURE 0
#define PIO_LED_EDGE_TYPE "NONE"
#define PIO_LED_IRQ_TYPE "NONE"
#define PIO_LED_FREQ 50000000

/*
 * tri_state_bridge_0 configuration
 *
 */

#define TRI_STATE_BRIDGE_0_NAME "/dev/tri_state_bridge_0"
#define TRI_STATE_BRIDGE_0_TYPE "altera_avalon_tri_state_bridge"

/*
 * sram_256x32bit_0 configuration
 *
 */

#define SRAM_256X32BIT_0_NAME "/dev/sram_256x32bit_0"
#define SRAM_256X32BIT_0_TYPE "sram_256x32bit"
#define SRAM_256X32BIT_0_BASE 0x00800000
#define SRAM_256X32BIT_0_SPAN 1048576
#define SRAM_256X32BIT_0_HDL_PARAMETERS ""

/*
 * sdram_0 configuration
 *
 */

#define SDRAM_0_NAME "/dev/sdram_0"
#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_0_BASE 0x01000000
#define SDRAM_0_SPAN 16777216
#define SDRAM_0_REGISTER_DATA_IN 1
#define SDRAM_0_SIM_MODEL_BASE 1
#define SDRAM_0_SDRAM_DATA_WIDTH 32
#define SDRAM_0_SDRAM_ADDR_WIDTH 12
#define SDRAM_0_SDRAM_ROW_WIDTH 12
#define SDRAM_0_SDRAM_COL_WIDTH 8
#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_0_SDRAM_NUM_BANKS 4
#define SDRAM_0_REFRESH_PERIOD 15.625
#define SDRAM_0_POWERUP_DELAY 100
#define SDRAM_0_CAS_LATENCY 3
#define SDRAM_0_T_RFC 70
#define SDRAM_0_T_RP 20
#define SDRAM_0_T_MRD 3
#define SDRAM_0_T_RCD 20
#define SDRAM_0_T_AC 5.5
#define SDRAM_0_T_WR 14
#define SDRAM_0_INIT_REFRESH_COMMANDS 2
#define SDRAM_0_INIT_NOP_DELAY 0
#define SDRAM_0_SHARED_DATA 0
#define SDRAM_0_STARVATION_INDICATOR 0
#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_0_IS_INITIALIZED 1
#define SDRAM_0_SDRAM_BANK_WIDTH 2

/*
 * spi_0 configuration
 *
 */

#define SPI_0_NAME "/dev/spi_0"
#define SPI_0_TYPE "altera_avalon_spi"
#define SPI_0_BASE 0x00900820
#define SPI_0_SPAN 32
#define SPI_0_IRQ 2
#define SPI_0_DATABITS 8
#define SPI_0_TARGETCLOCK 128
#define SPI_0_CLOCKUNITS "kHz"
#define SPI_0_CLOCKMULT 1000
#define SPI_0_NUMSLAVES 1
#define SPI_0_ISMASTER 1
#define SPI_0_CLOCKPOLARITY 0
#define SPI_0_CLOCKPHASE 0
#define SPI_0_LSBFIRST 0
#define SPI_0_EXTRADELAY 0
#define SPI_0_TARGETSSDELAY 100
#define SPI_0_DELAYUNITS "us"
#define SPI_0_DELAYMULT "1e-006"
#define SPI_0_CLOCKUNIT "kHz"
#define SPI_0_DELAYUNIT "us"
#define SPI_0_PREFIX "spi_"

/*
 * audio_dac_fifo_0 configuration
 *
 */

#define AUDIO_DAC_FIFO_0_NAME "/dev/audio_dac_fifo_0"
#define AUDIO_DAC_FIFO_0_TYPE "audio_dac_fifo"
#define AUDIO_DAC_FIFO_0_BASE 0x009008C0
#define AUDIO_DAC_FIFO_0_SPAN 4

/*
 * AUD_FULL configuration
 *
 */

#define AUD_FULL_NAME "/dev/AUD_FULL"
#define AUD_FULL_TYPE "altera_avalon_pio"
#define AUD_FULL_BASE 0x00900870
#define AUD_FULL_SPAN 16
#define AUD_FULL_DO_TEST_BENCH_WIRING 0
#define AUD_FULL_DRIVEN_SIM_VALUE 0x0000
#define AUD_FULL_HAS_TRI 0
#define AUD_FULL_HAS_OUT 0
#define AUD_FULL_HAS_IN 1
#define AUD_FULL_CAPTURE 0
#define AUD_FULL_EDGE_TYPE "NONE"
#define AUD_FULL_IRQ_TYPE "NONE"
#define AUD_FULL_FREQ 50000000

/*
 * SD_CS configuration
 *
 */

#define SD_CS_NAME "/dev/SD_CS"
#define SD_CS_TYPE "altera_avalon_pio"
#define SD_CS_BASE 0x00900880
#define SD_CS_SPAN 16
#define SD_CS_DO_TEST_BENCH_WIRING 0
#define SD_CS_DRIVEN_SIM_VALUE 0x0000
#define SD_CS_HAS_TRI 0
#define SD_CS_HAS_OUT 1
#define SD_CS_HAS_IN 0
#define SD_CS_CAPTURE 0
#define SD_CS_EDGE_TYPE "NONE"
#define SD_CS_IRQ_TYPE "NONE"
#define SD_CS_FREQ 50000000

/*
 * SD_PWR configuration
 *
 */

#define SD_PWR_NAME "/dev/SD_PWR"
#define SD_PWR_TYPE "altera_avalon_pio"
#define SD_PWR_BASE 0x00900890
#define SD_PWR_SPAN 16
#define SD_PWR_DO_TEST_BENCH_WIRING 0
#define SD_PWR_DRIVEN_SIM_VALUE 0x0000
#define SD_PWR_HAS_TRI 0
#define SD_PWR_HAS_OUT 1
#define SD_PWR_HAS_IN 0
#define SD_PWR_CAPTURE 0
#define SD_PWR_EDGE_TYPE "NONE"
#define SD_PWR_IRQ_TYPE "NONE"
#define SD_PWR_FREQ 50000000

/*
 * tri_state_bridge_1 configuration
 *
 */

#define TRI_STATE_BRIDGE_1_NAME "/dev/tri_state_bridge_1"
#define TRI_STATE_BRIDGE_1_TYPE "altera_avalon_tri_state_bridge"

/*
 * cfi_flash_0 configuration
 *
 */

#define CFI_FLASH_0_NAME "/dev/cfi_flash_0"
#define CFI_FLASH_0_TYPE "altera_avalon_cfi_flash"
#define CFI_FLASH_0_BASE 0x00000000
#define CFI_FLASH_0_SPAN 8388608
#define CFI_FLASH_0_SETUP_VALUE 40
#define CFI_FLASH_0_WAIT_VALUE 160
#define CFI_FLASH_0_HOLD_VALUE 40
#define CFI_FLASH_0_TIMING_UNITS "ns"
#define CFI_FLASH_0_UNIT_MULTIPLIER 1
#define CFI_FLASH_0_SIZE 8388608

/*
 * i2c_clk configuration
 *
 */

#define I2C_CLK_NAME "/dev/i2c_clk"
#define I2C_CLK_TYPE "altera_avalon_pio"
#define I2C_CLK_BASE 0x009008A0
#define I2C_CLK_SPAN 16
#define I2C_CLK_DO_TEST_BENCH_WIRING 0
#define I2C_CLK_DRIVEN_SIM_VALUE 0x0000
#define I2C_CLK_HAS_TRI 1
#define I2C_CLK_HAS_OUT 0
#define I2C_CLK_HAS_IN 0
#define I2C_CLK_CAPTURE 0
#define I2C_CLK_EDGE_TYPE "NONE"
#define I2C_CLK_IRQ_TYPE "NONE"
#define I2C_CLK_FREQ 50000000

/*
 * i2c_sda configuration
 *
 */

#define I2C_SDA_NAME "/dev/i2c_sda"
#define I2C_SDA_TYPE "altera_avalon_pio"
#define I2C_SDA_BASE 0x009008B0
#define I2C_SDA_SPAN 16
#define I2C_SDA_DO_TEST_BENCH_WIRING 0
#define I2C_SDA_DRIVEN_SIM_VALUE 0x0000
#define I2C_SDA_HAS_TRI 1
#define I2C_SDA_HAS_OUT 0
#define I2C_SDA_HAS_IN 0
#define I2C_SDA_CAPTURE 0
#define I2C_SDA_EDGE_TYPE "NONE"
#define I2C_SDA_IRQ_TYPE "NONE"
#define I2C_SDA_FREQ 50000000

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 4
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SRAM_256X32BIT_0
#define ALT_RODATA_DEVICE     SRAM_256X32BIT_0
#define ALT_RWDATA_DEVICE     SRAM_256X32BIT_0
#define ALT_EXCEPTIONS_DEVICE SDRAM_0
#define ALT_RESET_DEVICE      CFI_FLASH_0


#endif /* __SYSTEM_H_ */