huo.vhd

来自「实现6位频率计」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HUO IS 
PORT(CLR11:IN STD_LOGIC;
     CARRY_OUT11:IN STD_LOGIC;
     CLRR:OUT STD_LOGIC);
END HUO;
ARCHITECTURE behav OF HUO IS
BEGIN
 PROCESS(CLR11,CARRY_OUT11)
BEGIN
IF CARRY_OUT11='1' OR CLR11='1' 
   THEN CLRR<='1';
ELSE CLRR<='0';
    END IF;
   END PROCESS;
END behav;