counter32b.vhd

来自「实现6位频率计」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNTER32B IS
  PORT (CLK:IN STD_LOGIC;
        CLR:IN STD_LOGIC;
        ENA:IN STD_LOGIC;
        CQ:OUT INTEGER RANGE 0 TO 15;
        CARRY_OUT:OUT STD_LOGIC);
  END COUNTER32B;
ARCHITECTURE behav OF COUNTER32B IS
   SIGNAL CQI:INTEGER RANGE 0 TO 15;
BEGIN
PROCESS(CLK,CLR,ENA)
BEGIN
   IF CLR='1'THEN CQI<=0;
   ELSIF CLK'EVENT AND CLK='1'THEN
    IF ENA='1'THEN
      IF CQI<9 THEN CQI<=CQI+1;
      ELSE CQI<=0; END IF;
    END IF;
   END IF;
END PROCESS;
PROCESS(CQI)
BEGIN
   IF CQI=9 THEN CARRY_OUT<='1';
   ELSE CARRY_OUT<='0';END IF;
END PROCESS;
CQ<=CQI;
END behav;