ftctrl.vhd

来自「实现6位频率计」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FTCTRL IS
   PORT  (CLK:IN STD_LOGIC;
          TSTEN:OUT STD_LOGIC;
          CLR_CNT:OUT STD_LOGIC;
          LOAD:OUT STD_LOGIC );
END FTCTRL;
ARCHITECTURE behav OF FTCTRL IS
   SIGNAL Div2CLK :STD_LOGIC;
BEGIN
   PROCESS(CLK)
   BEGIN
      IF CLK'EVENT AND CLK='1'THEN
         Div2CLK<=NOT Div2CLK;
      END IF;
END PROCESS;
PROCESS (CLK,Div2CLK)
BEGIN
IF CLK='0' AND Div2CLK='0' THEN CLR_CNT<='1';
   ELSE CLR_CNT<='0';END IF;
END PROCESS;
LOAD <= NOT Div2CLK; TSTEN<=Div2CLK;
END behav;