lcd_s_test.v

来自「LED驱动」· Verilog 代码 · 共 30 行

module  LCD_S_TEST;
    reg      CLK, CLR;
    reg      [3:0] NUMW, NUMQ, NUMB, NUMS, NUMG;      
    wire     PH;
    wire     [3:0] P;        // p[0]=pa, p[1]=pb, p[2]=pc, p[3]=pd 
    wire     [3:0] DP;       // dp[0]=1dp, dp[1]=2dp, dp[2]=3dp, dp[3]=4dp 
    wire     [4:0] LD;       // ld[0]=1ld, ld[1]=2ld, ld[2]=3ld, ld[3]=4ld, ld[4]=5ld

    LCD_S  LCD_S (CLK, CLR, NUMW, NUMQ, NUMB, NUMS, NUMG, PH, P, DP, LD);

    always  #5  CLK=~CLK;
 
    initial 
      begin
        CLK=0; CLR=1; 
        NUMW=4'b0001; //1
        NUMQ=4'b0011;    //3
        NUMB=4'b0110;    //6
        NUMS=4'b1001;    //9
        NUMG=4'b1000;    //8
      #3   CLR=0;
      #3   CLR=1;
      #80  $finish;
     end
endmodule