📄 wm8753.h
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#define WM8753_MICMUX_MIC2 ((WM_REGVAL)(2U << 4)) /* 10: Sidetone = Mic 2 preamp output */
#define WM8753_MICMUX_RIGHT_PGA ((WM_REGVAL)(3U << 4)) /* 11: Sidetone = Right PGA output */
#define WM8753_LINEALC ((WM_REGVAL)(1U << 3)) /* LINEALC: Line mix selected into ALC mix */
#define WM8753_MIC2ALC ((WM_REGVAL)(1U << 2)) /* MIC2ALC: Mic 2 selected into ALC mix */
#define WM8753_MIC1ALC ((WM_REGVAL)(1U << 1)) /* MIC1ALC: Mic 1 selected into ALC mix */
#define WM8753_RXALC ((WM_REGVAL)(1U << 0)) /* RXALC: RX selected into ALC mix */
/*
* IN volumes (0x31/0x32)
*
* 11_1111 = +30dB
* ... (0.75dB steps)
* 00_0000 = -17.25dB
*
*/
#define WM8753_INVOL_MUTE ((WM_REGVAL)(1U << 7)) /* LINMUTE/RINMUTE */
#define WM8753_INVOL_ZEROCROSS ((WM_REGVAL)(1U << 6)) /* LZCEN/RZCEN */
#define WM8753_INVOL_MASK 0x03F /* LINVOL/RINVOL */
#define WM8753_INVOL_MAX 0x3F
#define WM8753_INVOL_MIN 0x00
#define WM8753_INVOL_RANGE (WM8753_INVOL_MAX - WM8753_INVOL_MIN)
#define WM8753_INVOL_0DB 0x17
#define WM8753_INVOL(_dB) (WM8753_INVOL_0DB + ( (4*(_dB)) / 3 ) )
/*
* Mic Bias comp control ( 0x33 )
*/
/*
* CLOCK control (0x34)
*/
#define WM8753_VXCLK_DIV_MASK ((WM_REGVAL)(7U << 6)) /* PCMDIV - [8:6] */
#define WM8753_VXCLK_DIV_1 ((WM_REGVAL)(0U << 6)) /* 000: divide by 1 */
#define WM8753_VXCLK_DIV_2 ((WM_REGVAL)(4U << 6)) /* 100: divide by 2 */
#define WM8753_VXCLK_DIV_3 ((WM_REGVAL)(2U << 6)) /* 010: divide by 3 */
#define WM8753_VXCLK_DIV_4 ((WM_REGVAL)(5U << 6)) /* 101: divide by 4 */
#define WM8753_VXCLK_DIV_5_5 ((WM_REGVAL)(3U << 6)) /* 011: divide by 5.5 */
#define WM8753_VXCLK_DIV_6 ((WM_REGVAL)(6U << 6)) /* 110: divide by 6 */
#define WM8753_VXCLK_DIV_8 ((WM_REGVAL)(7U << 6)) /* 111: divide by 8 */
#define WM8753_SWITCH_MCLK ((WM_REGVAL)(0U << 5)) /* SLWCLK - timeout and headphone switch from MCLK */
#define WM8753_SWITCH_PCMCLK ((WM_REGVAL)(1U << 5)) /* SLWCLK - timeout and headphone switch from PCMCLK */
#define WM8753_MCLKSEL_MASK ((WM_REGVAL)(1U << 4)) /* MCLKSEL: [4] */
#define WM8753_MCLKSEL_PCMCLK ((WM_REGVAL)(0U << 4)) /* MCLKSEL: Master clock for HIFI from MCLK pin */
#define WM8753_MCLKSEL_PLL1 ((WM_REGVAL)(1U << 4)) /* MCLKSEL: Master clock for HIFI from PLL1 (instead of MCLK pin) */
#define WM8753_PCMCLKSEL_MASK ((WM_REGVAL)(1U << 3)) /* PCMCLKSEL: [3] */
#define WM8753_PCMCLKSEL_PCMCLK ((WM_REGVAL)(0U << 3)) /* PCMCLKSEL: Master clock for Voice from MCLK pin */
#define WM8753_PCMCLKSEL_PLL2 ((WM_REGVAL)(1U << 3)) /* PCMCLKSEL: Master clock for Voice from PLL2 (instead of MCLK pin) */
#define WM8753_VXCLOCK_MASK ((WM_REGVAL)(1U << 2)) /* CLKEQ: [2] */
#define WM8753_VXCLOCK_PLL2 ((WM_REGVAL)(0U << 2)) /* CLKEQ: Voice clock from PCMCLK or PLL2 */
#define WM8753_VXCLOCK_PCM ((WM_REGVAL)(0U << 2)) /* CLKEQ: Voice clock from PCMCLK or PLL2 */
#define WM8753_VXCLOCK_HIFI ((WM_REGVAL)(1U << 2)) /* CLKEQ: Voice clock same as HiFi clock */
#define WM8753_GP1CLK1_MASK ((WM_REGVAL)(1U << 1)) /* GP1CLK1SEL: [1] */
#define WM8753_GP1CLK1_CLOCK ((WM_REGVAL)(1U << 1)) /* GP1CLK1SEL: 0 = GP1, 1 = CLK1 */
#define WM8753_GP1CLK1_GPIO ((WM_REGVAL)(0U << 1)) /* GP1CLK1SEL: 0 = GP1, 1 = CLK1 */
#define WM8753_GP2CLK2_MASK ((WM_REGVAL)(1U << 0)) /* GP2CLK2SEL: [0] */
#define WM8753_GP2CLK2_CLOCK ((WM_REGVAL)(1U << 0)) /* GP2CLK2SEL: 0 = GP1, 1 = CLK1 */
#define WM8753_GP2CLK2_GPIO ((WM_REGVAL)(0U << 0)) /* GP2CLK2SEL: 0 = GP1, 1 = CLK1 */
/*
* PLL CONTROL1 (PLL1:0x35/PLL2:0x39)
*/
#define WM8753_CLOCKOUT_MCLK ((WM_REGVAL)(0U << 5)) /* CLK1SEL/CLK2SEL: CLKOUT from MCLK */
#define WM8753_CLOCKOUT_PLL ((WM_REGVAL)(1U << 5)) /* CLK1SEL/CLK2SEL: CLKOUT from PLL */
#define WM8753_PLLCLOCK_DIV2 ((WM_REGVAL)(1U << 4)) /* CLK1DIV2/CLK2DIV2: CLKOUT divide by 2 */
#define WM8753_MCLK_DIV2 ((WM_REGVAL)(1U << 3)) /* MCLK1DIV2/MCLK2DIV2: MCLK divide by 2 */
#define WM8753_PLLOUT_DIV2 ((WM_REGVAL)(1U << 2)) /* PLL1DIV2/PLL2DIV2: PLL output divide by 2 */
#define WM8753_PLL_ACTIVE ((WM_REGVAL)(1U << 1)) /* PLL1RB/PLL2RB: "reset bar" = PLL active */
#define WM8753_PLL_ENABLE ((WM_REGVAL)(1U << 0)) /* PLL1EN/PLL2EN: PLL enabled */
/*
* PLL CONTROL2/3/4 (PLL1: 0x36/7/8 & PLL2: 0x3A/B/C)
*/
#define WM8753_PLL_N_MASK ((WM_REGVAL)(0xFU << 5)) /* PLL1N/PLL2N - [8:5] - in reg 2*/
#define WM8753_PLL_N(_n) ((WM_REGVAL)((_n) << 5))
#define WM8753_PLL_K2_MASK 0x00F /* PLL1K/PLL2K[21:18] - in reg 2 */
#define WM8753_PLL_K2(_k) (((_k) & 0x3C0000) >> 18) /* reg 2 bits - [21:18] */
#define WM8753_PLL_K3(_k) (((_k) & 0x03FE00) >> 9) /* reg 3 bits - [17:9] */
#define WM8753_PLL_K4(_k) (((_k) & 0x0001FF)) /* reg 4 bits - [8:0] */
#define WM8753_PLL_R2VAL(_n, _k) (WM8753_PLL_N(_n) | WM8753_PLL_K2(_k))
#define WM8753_PLL_R3VAL(_n, _k) (WM8753_PLL_K3(_k))
#define WM8753_PLL_R4VAL(_n, _k) (WM8753_PLL_K4(_k))
/*
* 0x3D
#define WM8753_BIAS_CONTROL 0x3D
*/
/*
* 0x3E is undefined
*/
/*
* ADD_CONTROL_2 (0x3F)
*/
#define WM8753_OUT4SEL_MASK ((WM_REGVAL)(3U << 7)) /* OUT4SW - [8:7] */
#define WM8753_OUT4SEL_VREF ((WM_REGVAL)(0U << 7)) /* 00: VREF */
#define WM8753_OUT4SEL_RECMIX ((WM_REGVAL)(1U << 7)) /* 01: Record Mixer */
#define WM8753_OUT4SEL_LOUT2 ((WM_REGVAL)(2U << 7)) /* 10: LOUT2 */
#define WM8753_THERMALSHUT_OUTPUTS ((WM_REGVAL)(1U << 6)) /* TSDADEN: Thermal shutdown shuts down */
/* speaker and headphone outputs */
#define WM8753_FULL_OUTPUT_BIAS ((WM_REGVAL)(0U << 1)) /* OPBIASX0P5: 1x Analogue output bias current */
#define WM8753_HALF_OUTPUT_BIAS ((WM_REGVAL)(1U << 1)) /* OPBIASX0P5: 0.5x Analogue output bias current */
#define WM8753_FULL_DAC_MIXER_BIAS ((WM_REGVAL)(0U << 0)) /* DMBIASX0P5: 1x DAC/Mixer bias current */
#define WM8753_HALF_DAC_MIXER_BIAS ((WM_REGVAL)(1U << 0)) /* DMBIASX0P5: 0.5x DAC/Mixer bias current */
unsigned int WM8753_Codec_Init_Table[][2] =
{
#if 1
{ 0x1f, 0x000 }, // R31
{ 0x01, 0x000 }, // R01
{ 0x02, 0x000 }, // R02
{ 0x03, 0x00a }, // R03
{ 0x04, 0x002 }, // R04
// { 0x05, 0x033 }, // R05
{ 0x05, 0x008 }, // R05
// { 0x05, 0x00b }, // R05 Interface Control IFMODE=10:Hifi, VXFSOE=0, LRCOE=0
// { 0x06, 0x038 }, // R06
{ 0x06, 0x022 }, // R06 44.1 on 384fs
{ 0x07, 0x0a7 }, // R07
{ 0x08, 0x1ff }, // R08
{ 0x09, 0x1ff }, // R09
{ 0x0a, 0x00f }, // R10
{ 0x0b, 0x00f }, // R11
// for line input, ALC off
{ 0x0c, 0x07b }, // R12, ALC Control 1, ALCSEL 0:off,
{ 0x0d, 0x000 }, // R13
{ 0x0e, 0x032 }, // R14
{ 0x0f, 0x000 }, // R15
{ 0x10, 0x1c3 }, // R16
{ 0x11, 0x1c3 }, // R17
{ 0x12, 0x0c0 }, // R18
{ 0x13, 0x000 }, // R19
// { 0x14, 0x0cc }, // R20 Power Management 1, VMIDSEL=50kOhm(01),VREF,DACL,DACR
{ 0x14, 0x0ec }, // R20 Power Management 1, VMIDSEL=50kOhm(01),VREF,MICB,DACL,DACR
// { 0x15, 0x000 }, // R21 Power Management 2, All Off
#if 0
{ 0x15, 0x1ff }, // R21 Pwr_mgt2 all enable
{ 0x16, 0x1ff }, // R22 Pwr_mgt3
{ 0x17, 0x1ff }, // R23 Pwr_mgt4
#else
{ 0x15, 0x00d }, // R21 Power Management 2, ADCL, ADCR, LINEMIX
{ 0x16, 0x180 }, // R22 Power Management 3, LOUT1, ROUT1
{ 0x17, 0x003 }, // R23 Power Management 4, RIGHTMIX, LEFTMIX
#endif
{ 0x18, 0x000 }, // R24
{ 0x19, 0x000 }, // R25
{ 0x1a, 0x000 }, // R26
{ 0x1b, 0x000 }, // R27
{ 0x1c, 0x000 }, // R28
{ 0x20, 0x055 }, // R32
{ 0x21, 0x005 }, // R33
{ 0x22, 0x150 }, // R34
{ 0x23, 0x055 }, // R35
{ 0x24, 0x150 }, // R36
{ 0x25, 0x055 }, // R37
{ 0x26, 0x050 }, // R38
{ 0x27, 0x055 }, // R39
{ 0x28, 0x15f }, // R40
{ 0x29, 0x15f }, // R41
{ 0x2a, 0x15f }, // R42
{ 0x2b, 0x15f }, // R43
{ 0x2c, 0x079 }, // R44
{ 0x2d, 0x004 }, // R45
// { 0x2e, 0x000 }, // R46
{ 0x2e, 0x005 }, // R46 ADC Input Mode, Stereo, LINE1, LINE2
{ 0x2f, 0x000 }, // R47 Input Control, LMSEL=LINE1+LINE2, MM=LineMixOutput, RM=LINE2, LM=LINE1
{ 0x30, 0x000 }, // R48
{ 0x31, 0x13f }, // R49 Left Input Volume
{ 0x32, 0x13f }, // R50 Right Input Volume
{ 0x33, 0x000 }, // R51 Mic Bias comp control
{ 0x34, 0x004 }, // R52
{ 0x35, 0x000 }, // R53
{ 0x36, 0x083 }, // R54
{ 0x37, 0x024 }, // R55
{ 0x38, 0x1ba }, // R56
{ 0x39, 0x000 }, // R57
{ 0x3a, 0x083 }, // R58
{ 0x3b, 0x024 }, // R59
{ 0x3c, 0x1ba }, // R60
{ 0x3d, 0x000 }, // R61
{ 0x3f, 0x000 }, // R62
#else
{ 0x1f, 0x000 }, // R31
{ 0x01, 0x000 }, // R01
{ 0x02, 0x000 }, // R02
{ 0x03, 0x00a }, // R03
{ 0x04, 0x002 }, // R04
{ 0x05, 0x033 }, // R05
// { 0x06, 0x038 }, // R06
{ 0x06, 0x022 }, // R06 44.1 on 384fs
{ 0x07, 0x0a7 }, // R07
{ 0x08, 0x1ff }, // R08
{ 0x09, 0x1ff }, // R09
{ 0x0a, 0x00f }, // R10
{ 0x0b, 0x00f }, // R11
{ 0x0c, 0x07b }, // R12
{ 0x0d, 0x000 }, // R13
{ 0x0e, 0x032 }, // R14
{ 0x0f, 0x000 }, // R15
{ 0x10, 0x0c3 }, // R16
{ 0x11, 0x0c3 }, // R17
{ 0x12, 0x0c0 }, // R18
{ 0x13, 0x000 }, // R19
{ 0x14, 0x0cc }, // R20 Power Management 1, VMIDSEL=50kOhm(01),VREF,DACL,DACR
// { 0x14, 0x0ec }, // R20 Power Management 1, VMIDSEL=50kOhm(01),VREF,MICB,DACL,DACR
// { 0x15, 0x000 }, // R21 Power Management 2, All Off
{ 0x15, 0x00d }, // R21 Power Management 2, ADCL, ADCR, LINEMIX
{ 0x16, 0x180 }, // R22 Power Management 3, LOUT1, ROUT1
{ 0x17, 0x003 }, // R23 Power Management 4, RIGHTMIX, LEFTMIX
{ 0x18, 0x000 }, // R24
{ 0x19, 0x000 }, // R25
{ 0x1a, 0x000 }, // R26
{ 0x1b, 0x000 }, // R27
{ 0x1c, 0x000 }, // R28
{ 0x20, 0x055 }, // R32
{ 0x21, 0x005 }, // R33
{ 0x22, 0x150 }, // R34
{ 0x23, 0x055 }, // R35
{ 0x24, 0x150 }, // R36
{ 0x25, 0x055 }, // R37
{ 0x26, 0x050 }, // R38
{ 0x27, 0x055 }, // R39
{ 0x28, 0x15f }, // R40
{ 0x29, 0x15f }, // R41
{ 0x2a, 0x15f }, // R42
{ 0x2b, 0x15f }, // R43
{ 0x2c, 0x079 }, // R44
{ 0x2d, 0x004 }, // R45
// { 0x2e, 0x000 }, // R46
{ 0x2e, 0x005 }, // R46 ADC Input Mode, Stereo, LINE1, LINE2
{ 0x2f, 0x000 }, // R47 Input Control, LMSEL=LINE1+LINE2, MM=LineMixOutput, RM=LINE2, LM=LINE1
{ 0x30, 0x000 }, // R48
{ 0x31, 0x137 }, // R49 Left Input Volume
{ 0x32, 0x137 }, // R50 Right Input Volume
{ 0x33, 0x000 }, // R51 Mic Bias comp control
{ 0x34, 0x004 }, // R52
{ 0x35, 0x000 }, // R53
{ 0x36, 0x083 }, // R54
{ 0x37, 0x024 }, // R55
{ 0x38, 0x1ba }, // R56
{ 0x39, 0x000 }, // R57
{ 0x3a, 0x083 }, // R58
{ 0x3b, 0x024 }, // R59
{ 0x3c, 0x1ba }, // R60
{ 0x3d, 0x000 }, // R61
{ 0x3f, 0x000 }, // R62
#endif
};
#endif /* __WM8753REGISTERDEFS_H__ */
/*------------------------------ END OF FILE ---------------------------------*/
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