wm8753.h

SAMSUNG S3C6410 CPU BSP for winmobile6

/*
 * 0x0A - 0x0B
#define WM8753_BASS_CONTROL                         0x0A
#define WM8753_TREBLE_CONTROL                       0x0B
*/

/*
 * ALC and noise gate - 0xC - 0xF
 */

/* ALC Control 1 - 0xC */
#define WM8753_ALC_LEVEL_MASK       ((WM_REGVAL)(0xF << 0)) /* ALCL - [3:0] */
#define WM8753_ALC_LEVEL(_dB)       (((WM_REGVAL)(((_dB)+28.5)*2/3+0.5)) & WM8753_ALC_LEVEL_MASK)

#define WM8753_ALCVOL_MASK          ((WM_REGVAL)(7U << 4))  /* MAXGAIN - [6:4] */
#define WM8753_ALCVOL_30DB          ((WM_REGVAL)(7U << 4))  /* +30dB */
#define WM8753_ALCVOL_24DB          ((WM_REGVAL)(6U << 4))  /* +24dB */
#define WM8753_ALCVOL_18DB          ((WM_REGVAL)(5U << 4))  /* +18dB */
#define WM8753_ALCVOL_12DB          ((WM_REGVAL)(4U << 4))  /* +12dB */
#define WM8753_ALCVOL_6DB           ((WM_REGVAL)(3U << 4))  /* +6dB  */
#define WM8753_ALCVOL_0DB           ((WM_REGVAL)(2U << 4))  /*  0dB  */
#define WM8753_ALCVOL_M6DB          ((WM_REGVAL)(1U << 4))  /* -6dB  */
#define WM8753_ALCVOL_M12DB         ((WM_REGVAL)(0U << 4))  /* -12dB */
#define WM8753_ALCVOL(_dB)          ((WM_REGVAL)(((((int)(_dB)+12+3)/6) << 4 ) & WM8753_ALCVOL_MASK))

#define WM8753_ALCSEL_MASK          ((WM_REGVAL)(3U << 7))  /* ALCSEL - [8:7] */
#define WM8753_ALC_OFF              ((WM_REGVAL)(0U << 7))  /* ALC off (PGA from register) */
#define WM8753_ALC_RIGHT            ((WM_REGVAL)(1U << 7))  /* Right channel only */
#define WM8753_ALC_LEFT             ((WM_REGVAL)(2U << 7))  /* Left channel only */
#define WM8753_ALC_STEREO           ((WM_REGVAL)(3U << 7))  /* Stereo (PGA registers unused) */

/* ALC Control 2 - 0xD */
#define WM8753_HOLD_MASK            ((WM_REGVAL)(0xF << 0)) /* HLD - [3:0] */
#define WM8753_HOLD_0MS             ((WM_REGVAL)(0x0 << 0)) /* 0ms */
#define WM8753_HOLD_2_67MS          ((WM_REGVAL)(0x1 << 0)) /* 2.67ms */
#define WM8753_HOLD_5_33MS          ((WM_REGVAL)(0x2 << 0)) /* 5.33ms */
#define WM8753_HOLD_10_67MS         ((WM_REGVAL)(0x3 << 0)) /* 10.67ms */
#define WM8753_HOLD_21_33MS         ((WM_REGVAL)(0x4 << 0)) /* 21.33ms */
#define WM8753_HOLD_43MS            ((WM_REGVAL)(0x5 << 0)) /* 42.67ms */
#define WM8753_HOLD_85MS            ((WM_REGVAL)(0x6 << 0)) /* 85.33ms */
#define WM8753_HOLD_171MS           ((WM_REGVAL)(0x7 << 0)) /* 170.67ms */
#define WM8753_HOLD_341MS           ((WM_REGVAL)(0x8 << 0)) /* 341.33ms */
#define WM8753_HOLD_683MS           ((WM_REGVAL)(0x9 << 0)) /* 682.67ms */
#define WM8753_HOLD_1_365S          ((WM_REGVAL)(0xA << 0)) /* 1.365s */
#define WM8753_HOLD_2_731S          ((WM_REGVAL)(0xB << 0)) /* 2.731s */
#define WM8753_HOLD_5_461S          ((WM_REGVAL)(0xC << 0)) /* 5.461s */
#define WM8753_HOLD_10_923S         ((WM_REGVAL)(0xD << 0)) /* 10.932s */
#define WM8753_HOLD_21_845S         ((WM_REGVAL)(0xE << 0)) /* 21.845s */
#define WM8753_HOLD_43_691S         ((WM_REGVAL)(0xF << 0)) /* 43.691s */

#define WM8753_ALC_SAMPLERATE_MASK  ((WM_REGVAL)(0xF << 4)) /* ALCSR - [7:4] */
#define WM8753_ALCSR_8K             ((WM_REGVAL)(0x6 << 4)) /* 8kHz */
#define WM8753_ALCSR_11K            ((WM_REGVAL)(0x8 << 4)) /* 11.025kHz */
#define WM8753_ALCSR_12K            ((WM_REGVAL)(0x8 << 4)) /* 12kHz */
#define WM8753_ALCSR_16K            ((WM_REGVAL)(0xA << 4)) /* 16kHz */
#define WM8753_ALCSR_22K            ((WM_REGVAL)(0xA << 4)) /* 22.05kHz */
#define WM8753_ALCSR_32K            ((WM_REGVAL)(0xC << 4)) /* 32kHz */
#define WM8753_ALCSR_44K            ((WM_REGVAL)(0x0 << 4)) /* 44.1kHz */
#define WM8753_ALCSR_48K            ((WM_REGVAL)(0x0 << 4)) /* 48kHz */
#define WM8753_ALCSR_88K            ((WM_REGVAL)(0xE << 4)) /* 88.2kHz */
#define WM8753_ALCSR_96K            ((WM_REGVAL)(0xE << 4)) /* 96kHz */

#define WM8753_ALC_ZEROCROSS        ((WM_REGVAL)(1U << 8))  /* ALCZC */

/* ALC Control 3 - 0xE */
#define WM8753_ATTACK_MASK          ((WM_REGVAL)(0xF << 0)) /* ATK - [3:0] */
#define WM8753_ATTACK_6MS           ((WM_REGVAL)(0x0 << 0)) /* 6ms */
#define WM8753_ATTACK_12MS          ((WM_REGVAL)(0x1 << 0)) /* 12ms */
#define WM8753_ATTACK_24MS          ((WM_REGVAL)(0x2 << 0)) /* 24ms */
#define WM8753_ATTACK_48MS          ((WM_REGVAL)(0x3 << 0)) /* 48ms */
#define WM8753_ATTACK_96MS          ((WM_REGVAL)(0x4 << 0)) /* 96ms */
#define WM8753_ATTACK_192MS         ((WM_REGVAL)(0x5 << 0)) /* 192ms */
#define WM8753_ATTACK_384MS         ((WM_REGVAL)(0x6 << 0)) /* 384ms */
#define WM8753_ATTACK_768MS         ((WM_REGVAL)(0x7 << 0)) /* 768ms */
#define WM8753_ATTACK_1_54S         ((WM_REGVAL)(0x8 << 0)) /* 1536ms */
#define WM8753_ATTACK_3S            ((WM_REGVAL)(0x9 << 0)) /* 3.07s */
#define WM8753_ATTACK_6S            ((WM_REGVAL)(0xA << 0)) /* 6.14s */

#define WM8753_DECAY_MASK           ((WM_REGVAL)(0xF << 4)) /* DCY - [7:4] */
#define WM8753_DECAY_24MS           ((WM_REGVAL)(0x0 << 4)) /* 24ms */
#define WM8753_DECAY_48MS           ((WM_REGVAL)(0x1 << 4)) /* 48ms */
#define WM8753_DECAY_96MS           ((WM_REGVAL)(0x2 << 4)) /* 96ms */
#define WM8753_DECAY_192MS          ((WM_REGVAL)(0x3 << 4)) /* 192ms */
#define WM8753_DECAY_384MS          ((WM_REGVAL)(0x4 << 4)) /* 384ms */
#define WM8753_DECAY_768MS          ((WM_REGVAL)(0x5 << 4)) /* 768ms */
#define WM8753_DECAY_1_54S          ((WM_REGVAL)(0x6 << 4)) /* 1536ms */
#define WM8753_DECAY_3S             ((WM_REGVAL)(0x7 << 4)) /* 3.072s */
#define WM8753_DECAY_6S             ((WM_REGVAL)(0x8 << 4)) /* 6.144s */
#define WM8753_DECAY_12S            ((WM_REGVAL)(0x9 << 4)) /* 12.288s */
#define WM8753_DECAY_24S            ((WM_REGVAL)(0xA << 4)) /* 24.576s */

/* Noise Gate Control - 0xF */
#define WM8753_NOISE_GATE_ENABLE    ((WM_REGVAL)(1U << 0))  /* NGAT */

#define WM8753_NOISE_GATE_TYPE      ((WM_REGVAL)(1U << 1))  /* NGG */
#define WM8753_NOISE_GATE_CONSTANT  ((WM_REGVAL)(0U << 1))  /* PGA gain held constant */
#define WM8753_NOISE_GATE_MUTE      ((WM_REGVAL)(1U << 1))  /* mute ADC output */

#define WM8753_NG_THRESH_MASK       ((WM_REGVAL)(0x1F << 3))/* NGTH - [7:3] */
#define WM8753_NG_THRESH(_dB)       (((WM_REGVAL)(((_dB)+76.5)*2/3+0.5) << 3) & WM8753_NG_THRESH_MASK)

/*
 * Suggested ALC profiles - see application note WAN0140.
 * 
 * Voice: Stereo Max +30dB, target -12dB, 0ms hold, 192ms decay, 24ms attack
 * Music: Stereo Max +30dB, target -6dB, 341ms hold, 6s decay, 24ms attack
 * 
 * For both: Noise gate enabled, gain constant, threshold -76.5dB
 */
#define WM8753_ALC1_PROFILE_MASK    (WM8753_ALC_LEVEL_MASK | WM8753_ALCVOL_MASK)
#define WM8753_ALC2_PROFILE_MASK    (WM8753_HOLD_MASK | WM8753_ALC_ZEROCROSS)

/* Voice */
#define WM8753_ALCVOL_VOICE         WM8753_ALCVOL_30DB
#define WM8753_ALC_LEVEL_VOICE      WM8753_ALC_LEVEL(-12)
#define WM8753_ALCZC_VOICE          0
#define WM8753_HOLD_VOICE           WM8753_HOLD_0MS
#define WM8753_DECAY_VOICE          WM8753_DECAY_192MS
#define WM8753_ATTACK_VOICE         WM8753_ATTACK_24MS

#define WM8753_ALC1_VOICE           (WM8753_ALC_LEVEL_VOICE | WM8753_ALCVOL_VOICE)
#define WM8753_ALC2_VOICE           (WM8753_HOLD_VOICE | WM8753_ALCZC_VOICE)
#define WM8753_ALC3_VOICE           (WM8753_DECAY_VOICE | WM8753_ATTACK_VOICE)
#define WM8753_NOISE_GATE_VOICE     (WM8753_NOISE_GATE_ENABLE   |       \
                                     WM8753_NOISE_GATE_CONSTANT |       \
                                     WM8753_NG_THRESH(-76.5))

/* Music */
#define WM8753_ALCVOL_MUSIC         WM8753_ALCVOL_30DB
#define WM8753_ALC_LEVEL_MUSIC      WM8753_ALC_LEVEL(-6)
#define WM8753_ALCZC_MUSIC          WM8753_ALC_ZEROCROSS
#define WM8753_HOLD_MUSIC           WM8753_HOLD_341MS
#define WM8753_DECAY_MUSIC          WM8753_DECAY_6S
#define WM8753_ATTACK_MUSIC         WM8753_ATTACK_24MS

#define WM8753_ALC1_MUSIC           (WM8753_ALC_LEVEL_MUSIC | WM8753_ALCVOL_MUSIC)
#define WM8753_ALC2_MUSIC           (WM8753_HOLD_MUSIC | WM8753_ALCZC_MUSIC)
#define WM8753_ALC3_MUSIC           (WM8753_DECAY_MUSIC | WM8753_ATTACK_MUSIC)
#define WM8753_NOISE_GATE_MUSIC     (WM8753_NOISE_GATE          |       \
                                     WM8753_NOISE_GATE_CONSTANT |       \
                                     WM8753_NG_THRESH(-76.5))

/*
 * ADC_VOLUME (0x10/0x11)
 * See below DAC_VOLUME (0x8/0x9)
 */
 
/*
 * 0x12 - 0x13
#define WM8753_ADD_CONTROL_1                        0x12
#define WM8753_3D_CONTROL                           0x13
 */
 
/*
 * Power management (registers 14h, 15h, 16h and 17h).
 */
#define WM8753_MAX_POWER_REGS                       4

/* Power managment 1 (register 14h) */
#define WM8753_PWR1_DIGENB                          ((WM_REGVAL)(1U<<0))
#define WM8753_PWR1_DACR                            ((WM_REGVAL)(1U<<2))
#define WM8753_PWR1_DACL                            ((WM_REGVAL)(1U<<3))
#define WM8753_PWR1_HIFIDAC                         (WM8753_PWR1_DACR | \
                                                     WM8753_PWR1_DACL)
#define WM8753_PWR1_VXDAC                           ((WM_REGVAL)(1U<<4))
#define WM8753_PWR1_DACS                            (WM8753_PWR1_HIFIDAC | \
                                                     WM8753_PWR1_VXDAC )
#define WM8753_PWR1_MICB                            ((WM_REGVAL)(1U<<5))
#define WM8753_PWR1_VREF                            ((WM_REGVAL)(1U<<6))
#define WM8753_PWR1_VMIDSEL_DISABLE                 ((WM_REGVAL)(0U<<7))
#define WM8753_PWR1_VMIDSEL_50KOHM                  ((WM_REGVAL)(1U<<7))
#define WM8753_PWR1_VMIDSEL_500KOHM                 ((WM_REGVAL)(2U<<7))
#define WM8753_PWR1_VMIDSEL_5KOHM                   ((WM_REGVAL)(3U<<7))
#define WM8753_PWR1_VMIDSEL_MASK                    ((WM_REGVAL)(3U<<7))

/* Power managment 2 (register 15h) */
#define WM8753_PWR2_LINEMIX                         ((WM_REGVAL)(1U<<0))
#define WM8753_PWR2_RXMIX                           ((WM_REGVAL)(1U<<1))
#define WM8753_PWR2_ADCR                            ((WM_REGVAL)(1U<<2))
#define WM8753_PWR2_ADCL                            ((WM_REGVAL)(1U<<3))
#define WM8753_PWR2_PGAR                            ((WM_REGVAL)(1U<<4))
#define WM8753_PWR2_PGAL                            ((WM_REGVAL)(1U<<5))
#define WM8753_PWR2_PGA                             (WM8753_PWR2_PGAR       | \
                                                     WM8753_PWR2_PGAL)
#define WM8753_PWR2_ADC                             (WM8753_PWR2_ADCR       | \
                                                     WM8753_PWR2_ADCL       | \
                                                     WM8753_PWR2_PGA)
#define WM8753_PWR2_ALCMIX                          ((WM_REGVAL)(1U<<6))
#define WM8753_PWR2_MIX                             (WM8753_PWR2_LINEMIX    | \
                                                     WM8753_PWR2_RXMIX      | \
                                                     WM8753_PWR2_ALCMIX)
#define WM8753_PWR2_MICAMP2EN                       ((WM_REGVAL)(1U<<7))
#define WM8753_PWR2_MICAMP1EN                       ((WM_REGVAL)(1U<<8))
#define WM8753_PWR2_MICAMPEN                        (WM8753_PWR2_MICAMP2EN  | \
                                                     WM8753_PWR2_MICAMP1EN)

/* Power managment 3 (register 16h) */
#define WM8753_PWR3_MONO2                           ((WM_REGVAL)(1U<<1))
#define WM8753_PWR3_MONO1                           ((WM_REGVAL)(1U<<2))
#define WM8753_PWR3_OUT4                            ((WM_REGVAL)(1U<<3))
#define WM8753_PWR3_OUT3                            ((WM_REGVAL)(1U<<4))
#define WM8753_PWR3_ROUT2                           ((WM_REGVAL)(1U<<5))
#define WM8753_PWR3_LOUT2                           ((WM_REGVAL)(1U<<6))
#define WM8753_PWR3_ROUT1                           ((WM_REGVAL)(1U<<7))
#define WM8753_PWR3_LOUT1                           ((WM_REGVAL)(1U<<8))
#define WM8753_PWR3_OUTPUT                          (WM8753_PWR3_MONO2      | \
                                                     WM8753_PWR3_MONO1      | \
                                                     WM8753_PWR3_OUT4       | \
                                                     WM8753_PWR3_OUT3       | \
                                                     WM8753_PWR3_ROUT2      | \
                                                     WM8753_PWR3_LOUT2      | \
                                                     WM8753_PWR3_ROUT1      | \
                                                     WM8753_PWR3_LOUT1)

/* Power managment 4 (register 17h) */
#define WM8753_PWR4_LEFTMIX                         ((WM_REGVAL)(1U<<0))
#define WM8753_PWR4_RIGHTMIX                        ((WM_REGVAL)(1U<<1))
#define WM8753_PWR4_MONOMIX                         ((WM_REGVAL)(1U<<2))
#define WM8753_PWR4_RECMIX                          ((WM_REGVAL)(1U<<3))
#define WM8753_PWR4_MIX                             (WM8753_PWR4_LEFTMIX    | \
                                                     WM8753_PWR4_RIGHTMIX   | \
                                                     WM8753_PWR4_MONOMIX    | \
                                                     WM8753_PWR4_RECMIX)
/*
 * 0x18-0x21
#define WM8753_ID_REGISTER                          0x18
#define WM8753_INTERUPT_POLARITY                    0x19
#define WM8753_INTERUPT_ENABLE                      0x1A
#define WM8753_GPIO_CONTROL_1                       0x1B
#define WM8753_GPIO_CONTROL_2                       0x1C
#define WM8753_RESET                                0x1F
#define WM8753_RECORD_MIX_1                         0x20
#define WM8753_RECORD_MIX_2                         0x21
 */

/*
 * Interrupt Polarity (register 19h)
 */
#define WM8753_INT_POL_TSD							((WM_REGVAL)(1U<<7))
#define WM8753_INT_POL_HPSW							((WM_REGVAL)(1U<<6))
#define WM8753_INT_POL_GPIO5						((WM_REGVAL)(1U<<5))
#define WM8753_INT_POL_GPIO4						((WM_REGVAL)(1U<<4))
#define WM8753_INT_POL_GPIO3						((WM_REGVAL)(1U<<3))
#define WM8753_INT_POL_MICDET						((WM_REGVAL)(1U<<1))
#define WM8753_INT_POL_MICSSDET						((WM_REGVAL)(1U<<0))

/*
 * Interrupt Masks (register 1Ah)
 */
#define WM8753_INT_EN_TSD							((WM_REGVAL)(1U<<7))
#define WM8753_INT_EN_HPSW							((WM_REGVAL)(1U<<6))
#define WM8753_INT_EN_GPIO5							((WM_REGVAL)(1U<<5))
#define WM8753_INT_EN_GPIO4							((WM_REGVAL)(1U<<4))
#define WM8753_INT_EN_GPIO3							((WM_REGVAL)(1U<<3))
#define WM8753_INT_EN_MICDET						((WM_REGVAL)(1U<<1))
#define WM8753_INT_EN_MICSSDET						((WM_REGVAL)(1U<<0))

/*
 * Interrupt Control [1] (register 1Bh)
 */
#define WM8753_INT_CON_DIS							((WM_REGVAL)(0x00U<<7))
#define WM8753_INT_CON_OPEN_DRAIN_ACT_LOW			((WM_REGVAL)(0x01U<<7))
#define WM8753_INT_CON_ACT_HIGH						((WM_REGVAL)(0x02U<<7))
#define WM8753_INT_CON_ACT_LOW						((WM_REGVAL)(0x03U<<7))