wm8753.h

SAMSUNG S3C6410 CPU BSP for winmobile6

/*-----------------------------------------------------------------------------
 * Copyright (c) Wolfson Microelectronics plc.  All rights reserved.
 *
 * This software as well as any related documentation is furnished under 
 * license and may only be used or copied in accordance with the terms of the 
 * license. The information in this file is furnished for informational use 
 * only, is subject to change without notice, and should not be construed as 
 * a commitment by Wolfson Microelectronics plc. Wolfson Microelectronics plc
 * assumes no responsibility or liability for any errors or inaccuracies that
 * may appear in this document or any software that may be provided in
 * association with this document. 
 *
 * Except as permitted by such license, no part of this document may be 
 * reproduced, stored in a retrieval system, or transmitted in any form or by 
 * any means without the express written consent of Wolfson Microelectronics plc. 
 *
 * $Id: WM8753RegisterDefs.h 2361 2005-11-04 15:53:00Z ib $
 *
 * The registers on the Wolfson WM8753 device.
 *
 * Warning:
 *  This driver is specifically written for Wolfson Codecs. It is not a 
 *  general CODEC device driver.
 *
 *---------------------------------------------------------------------------*/
#ifndef __WM8753REGISTERDEFS_H__
#define __WM8753REGISTERDEFS_H__

typedef unsigned short WM_USHORT;   /* Do not use. Left in for backwards compatiblity only */

//typedef WM_USHORT				WM_REGTYPE;
typedef WM_USHORT				WM_REGVAL;

/* 
 * Include files
 */

/*
 * Register values.
 */
#define WM8753_DAC_CONTROL                          0x01
#define WM8753_ADC_CONTROL                          0x02
#define WM8753_VOICE_AUDIO_INTERFACE                0x03
#define WM8753_HIFI_AUDIO_INTERFACE                 0x04
#define WM8753_INTERFACE_CONTROL                    0x05
#define WM8753_SAMPLE_RATE_CTRL_1                   0x06
#define WM8753_SAMPLE_RATE_CTRL_2                   0x07
#define WM8753_LEFT_DAC_VOLUME                      0x08
#define WM8753_RIGHT_DAC_VOLUME                     0x09
#define WM8753_BASS_CONTROL                         0x0A
#define WM8753_TREBLE_CONTROL                       0x0B
#define WM8753_ALC_1                                0x0C
#define WM8753_ALC_2                                0x0D
#define WM8753_ALC_3                                0x0E
#define WM8753_NOISE_GATE                           0x0F
#define WM8753_LEFT_ADC_VOLUME                      0x10
#define WM8753_RIGHT_ADC_VOLUME                     0x11
#define WM8753_ADD_CONTROL_1                        0x12
#define WM8753_3D_CONTROL                           0x13
#define WM8753_PWR_MGMT_1                           0x14
#define WM8753_PWR_MGMT_2                           0x15
#define WM8753_PWR_MGMT_3                           0x16
#define WM8753_PWR_MGMT_4                           0x17
#define WM8753_ID_REGISTER                          0x18
#define WM8753_INTERUPT_POLARITY                    0x19
#define WM8753_INTERUPT_ENABLE                      0x1A
#define WM8753_GPIO_CONTROL_1                       0x1B
#define WM8753_GPIO_CONTROL_2                       0x1C
#define WM8753_RESET                                0x1F
#define WM8753_RECORD_MIX_1                         0x20
#define WM8753_RECORD_MIX_2                         0x21
#define WM8753_LEFT_OUT_MIX_1                       0x22
#define WM8753_LEFT_OUT_MIX_2                       0x23
#define WM8753_RIGHT_OUT_MIX_1                      0x24
#define WM8753_RIGHT_OUT_MIX_2                      0x25
#define WM8753_MONO_OUT_MIX_1                       0x26
#define WM8753_MONO_OUT_MIX_2                       0x27
#define WM8753_LOUT1_VOLUME                         0x28
#define WM8753_ROUT1_VOLUME                         0x29
#define WM8753_LOUT2_VOLUME                         0x2A
#define WM8753_ROUT2_VOLUME                         0x2B
#define WM8753_MONOOUT_VOLUME                       0x2C
#define WM8753_OUTPUT_CONTROL                       0x2D
#define WM8753_ADC_INPUT_MODE                       0x2E
#define WM8753_INPUT_CONTROL_1                      0x2F
#define WM8753_INPUT_CONTROL_2                      0x30
#define WM8753_LEFT_INPUT_VOLUME                    0x31
#define WM8753_RIGHT_INPUT_VOLUME                   0x32
#define WM8753_MIC_BIAS_COMP_CONTROL                0x33
#define WM8753_CLOCK_CONTROL                        0x34
#define WM8753_PLL1_CONTROL_1                       0x35
#define WM8753_PLL1_CONTROL_2                       0x36
#define WM8753_PLL1_CONTROL_3                       0x37
#define WM8753_PLL1_CONTROL_4                       0x38
#define WM8753_PLL2_CONTROL_1                       0x39
#define WM8753_PLL2_CONTROL_2                       0x3A
#define WM8753_PLL2_CONTROL_3                       0x3B
#define WM8753_PLL2_CONTROL_4                       0x3C
#define WM8753_BIAS_CONTROL                         0x3D
#define WM8753_ADD_CONTROL_2                        0x3F

#define WM8753_REGISTER_COUNT                       0x3C
#define WM8753_MAX_REGISTER                         WM8753_ADD_CONTROL_2

//#define WM8753_MAX_REGISTER_COUNT 					(WM8753_MAX_REGISTER + 1) //64

/* General volume defines */
#define WM8753_VOLUME_UPDATE        ((WM_REGVAL)(1U << 8))

/* DAC Control (0x01) */
#define WM8753_DACINV               ((WM_REGVAL)(1U << 6))   /* DACINV: DAC Phase Invert */
#define WM8753_DACMONOMIX_MASK      ((WM_REGVAL)(3U << 4))   /* DMONOMIX: [5:4] */
#define WM8753_DACMONOMIX_STEREO    ((WM_REGVAL)(0U << 4))   /* 00: stereo */
#define WM8753_DACMONOMIX_MONO_L    ((WM_REGVAL)(1U << 4))   /* 01: mono ((L+R)/2) into DACL, '0' into DACR */
#define WM8753_DACMONOMIX_MONO_R    ((WM_REGVAL)(2U << 4))   /* 10: mono ((L+R)/2) into DACR, '0' into DACL */
#define WM8753_DACMONOMIX_MONO_LR   ((WM_REGVAL)(3U << 4))   /* 11: mono ((L+R)/2) into DACL and DACR */
#define WM8753_DAC_SOFT_MUTE        ((WM_REGVAL)(1U << 3))   /* DACMU: Digital soft Mute */
#define WM8753_DEEMP_MASK           ((WM_REGVAL)(3U << 1))   /* DEEMPH: [2:1] */
#define WM8753_DEEMP_NONE           ((WM_REGVAL)(0U << 1))   /* 00: No De-emphasis */
#define WM8753_DEEMP_32KHZ          ((WM_REGVAL)(1U << 1))   /* 01: 32kHz sample rate */
#define WM8753_DEEMP_44_1KHZ        ((WM_REGVAL)(2U << 1))   /* 10: 44.1kHz sample rate */
#define WM8753_DEEMP_48KHZ          ((WM_REGVAL)(3U << 1))   /* 11: 48kHz sample rate */

/* ADC Control (0x02) */
#define WM8753_DATSEL_MASK          ((WM_REGVAL)(3U << 7))   /* DATSEL: [8:7] */
#define WM8753_DATSEL_L_R           ((WM_REGVAL)(0U << 7))   /* 00: left data = left ADC; right data = right ADC */
#define WM8753_DATSEL_L_L           ((WM_REGVAL)(1U << 7))   /* 01: left data = left ADC; right data = left ADC */
#define WM8753_DATSEL_R_R           ((WM_REGVAL)(2U << 7))   /* 10: left data = right ADC; right data = right ADC */
#define WM8753_DATSEL_R_L           ((WM_REGVAL)(3U << 7))   /* 11: left data = right ADC; right data = left ADC */
#define WM8753_ADCPOL_MASK          ((WM_REGVAL)(3U << 5))   /* ADCPOL: [6:5] */
#define WM8753_ADCPOL_NONE_INVERT   ((WM_REGVAL)(0U << 5))   /* 00: Polarity not inverted */
#define WM8753_ADCPOL_L_INVERT      ((WM_REGVAL)(1U << 5))   /* 01: Left polarity inverted */
#define WM8753_ADCPOL_R_INVERT      ((WM_REGVAL)(2U << 5))   /* 10: Right polarity inverted */
#define WM8753_ADCPOL_LR_INVERT     ((WM_REGVAL)(3U << 5))   /* 11: Left and Right polarity inverted */
#define WM8753_VXFILTER_HIFI        ((WM_REGVAL)(0U << 4))   /* VXFILT: ADC Filter - HiFi */
#define WM8753_VXFILTER_VOICE       ((WM_REGVAL)(1U << 4))   /* VXFILT: ADC Filter - Voice */
#define WM8753_HPMODE_MASK          ((WM_REGVAL)(3U << 2))   /* HPMODE: [3:2] */
#define WM8753_HPMODE_3_4HZ_48KHZ   ((WM_REGVAL)(0U << 2))   /* 00: 3.4Hz @ fs = 48kHz */
#define WM8753_HPMODE_82HZ_16KHZ    ((WM_REGVAL)(1U << 2))   /* 01: 82Hz @ fs = 16kHz (41Hz @ fs = 8kHz) */
#define WM8753_HPMODE_82HZ_8KHZ     ((WM_REGVAL)(2U << 2))   /* 10: 82Hz @ fs = 8kHz (164Hz @ fs = 16kHz) */
#define WM8753_HPMODE_170HZ_8KHZ    ((WM_REGVAL)(3U << 2))   /* 11: 170Hz @ fs = 8kHz (340Hz @ fs = 16kHz) */
#define WM8753_DC_OFFSET_CLEAR      ((WM_REGVAL)(0U << 1))   /* HPOR: Clear DC offset */
#define WM8753_DC_OFFSET_STORE      ((WM_REGVAL)(1U << 1))   /* HPOR: Store DC offset */
#define WM8753_HP_FILTER_DISABLE    ((WM_REGVAL)(1U << 0))   /* ADCHPD: ADC High Pass Filter (Digital) Disable */  
 
/*
 * Audio Interfaces - HIFI/VOICE interface control (0x03/0x04)
 */
#define WM8753_ADCDOP_MASK          ((WM_REGVAL)(1U << 8))   /* ADCDOP: Voice only: [8] */
#define WM8753_ADCDOP_ADCDAT_VXDOUT ((WM_REGVAL)(1U << 8))   /* ADCDOP: Voice only: ADC data output to ADCDAT and VXDOUT */
#define WM8753_ADCDOP_ADCDAT        ((WM_REGVAL)(0U << 8))   /* ADCDOP: Voice only: ADC data output to ADCDAT or VXDOUT as selected by IFMODE[1:0] */
#define WM8753_ADCDOP_VXDOUT        ((WM_REGVAL)(0U << 8))   /* ADCDOP: Voice only: ADC data output to ADCDAT or VXDOUT as selected by IFMODE[1:0] */
#define WM8753_DACCLKINV            ((WM_REGVAL)(1U << 7))   /* BCLKINV/VXCLKINV: VXCLK invert */
#define WM8753_BITCLKINV            WM8753_DACCLKINV
#define WM8753_VXCLKINV             WM8753_DACCLKINV

#define WM8753_MASTER               ((WM_REGVAL)(1U << 6))   /* MS/PMS: WM8753 is the master */
#define WM8753_SLAVE                ((WM_REGVAL)(0U << 6))   /* MS/PMS: WM8753 is the slave */

#define WM8753_HIFI_LR_SWAP         ((WM_REGVAL)(1U << 5))   /* LRSWAP: HIFI only: swap left and right channels */
#define WM8753_VOICE_MONO           ((WM_REGVAL)(1U << 5))   /* MONO: Voice only: output only on left channel */
#define WM8753_VOICE_LEFT_ONLY      WM8753_VOICE_MONO
#define WM8753_VOICE_BOTH           ((WM_REGVAL)(0U << 5))   /* MONO: Voice only: output left and right channels */

#define WM8753_DSP_MODE_MASK        ((WM_REGVAL)(1U << 4))   /* LRP: [4] DSP Mode */
#define WM8753_LRC_INVERT           ((WM_REGVAL)(1U << 4))   /* LRP: right, left and I2S: invert LRC polarity */
#define WM8753_DSP_MODE_A           ((WM_REGVAL)(0U << 4))   /* LRP: DSP mode A: 2nd BITCLK after LRC */
#define WM8753_DSP_MODE_B           ((WM_REGVAL)(1U << 4))   /* LRP: DSP mode B: 1st BITCLK after LRC */

#define WM8753_WORD_LENGTH_MASK     ((WM_REGVAL)(3U << 2))   /* WL - [3:2] data word length */
#define WM8753_WORD_LENGTH_16BIT    ((WM_REGVAL)(0U << 2))   /* 00: 16-bit word length */
#define WM8753_WORD_LENGTH_20BIT    ((WM_REGVAL)(1U << 2))   /* 01: 20-bit word length */
#define WM8753_WORD_LENGTH_24BIT    (((WM_REGVAL)2U << 2))   /* 10: 24-bit word length */
#define WM8753_WORD_LENGTH_32BIT    (((WM_REGVAL)3U << 2))   /* 11: 32-bit word length (not right-justified) */

#define WM8753_DATA_FORMAT_MASK     ((WM_REGVAL)(3U << 0))   /* FORMAT - [1:0] - data format */
#define WM8753_DATA_FORMAT_RJUST    ((WM_REGVAL)(0U << 0))   /* 00: right-justified */
#define WM8753_DATA_FORMAT_LJUST    ((WM_REGVAL)(1U << 0))   /* 01: left-justified */
#define WM8753_DATA_FORMAT_I2S      ((WM_REGVAL)(2U << 0))   /* 10: I2S */
#define WM8753_DATA_FORMAT_DSP      ((WM_REGVAL)(3U << 0))   /* 11: DSP mode */

/* INTERFACE_CONTROL (0x05) */
#define WM8753_VXCLK_ENABLE         ((WM_REGVAL)(0U << 7))   /* VXCLKTRI: VXCLK pin is input/output */
#define WM8753_VXCLK_TRISTATE       ((WM_REGVAL)(1U << 7))   /* VXCLKTRI: VXCLK pin is tristated */
#define WM8753_BITCLK_ENABLE        ((WM_REGVAL)(0U << 6))   /* BCLKTRI: BCLK pin is input/output */
#define WM8753_BITCLK_TRISTATE      ((WM_REGVAL)(1U << 6))   /* BCLKTRI: BCLK pin is tristated */
#define WM8753_VXDOUT_OUTPUT        ((WM_REGVAL)(0U << 5))   /* VXDTRI: VXDOUT pin is output */
#define WM8753_VXDOUT_TRISTATE      ((WM_REGVAL)(1U << 5))   /* VXDTRI: VXDOUT pin is tristated */
#define WM8753_ADCDAT_OUTPUT        ((WM_REGVAL)(0U << 4))   /* ADCTRI: ADCDATA pin is output */
#define WM8753_ADCDAT_TRISTATE      ((WM_REGVAL)(1U << 4))   /* ADCTRI: ADCDATA pin is tristated */

#define WM8753_INTERFACE_MODE_MASK  ((WM_REGVAL)(3U << 2))   /* IFMODE - [3:2]: */
#define WM8753_MODE_HIFI_VOICE      ((WM_REGVAL)(0U << 2))   /* 00: HIFI DAC + Voice codec */
#define WM8753_MODE_VOICE_ON_HIFI   ((WM_REGVAL)(1U << 2))   /* 01: Voice codec on HIFI interface */
#define WM8753_MODE_HIFI            ((WM_REGVAL)(2U << 2))   /* 10: HIFI ADC and DAC, no voice */
#define WM8753_MODE_HIFI_VXFS       ((WM_REGVAL)(3U << 2))   /* 11: HIFI using VXFS for ADC, no voice */
#define WM8753_VXFS_INPUT           ((WM_REGVAL)(0U << 1))   /* VXFSOE: VXFS pin is input in master mode */
#define WM8753_VXFS_OUTPUT          ((WM_REGVAL)(1U << 1))   /* VXFSOE: VXFS pin is output in master mode */
#define WM8753_LRC_INPUT            ((WM_REGVAL)(0U << 0))   /* LRCOE: LRC pin is input in master mode */
#define WM8753_LRC_OUTPUT           ((WM_REGVAL)(1U << 0))   /* LRCOE: LRC pin is output in master mode */
 
/*
 * SAMPLE_RATE_CTRL_1 (0x06)
 */
#define WM8753_SAMPLERATE_MASK      ((WM_REGVAL)(0x1FU << 1))/* SR - [5:1] */
#define WM8753_SAMPLERATE_SHIFT     1

#define WM8753_SAMPLE_CLOCK_MASK    ((WM_REGVAL)(1U << 0))   /* USB: [0] */
#define WM8753_SAMPLE_USB           ((WM_REGVAL)(1U << 0))   /* USB: USB mode */
#define WM8753_SAMPLE_NORMAL        ((WM_REGVAL)(0U << 0))   /* USB: normal mode */   
#define WM8753_SAMPLE_FEQUENCY_MASK ((WM_REGVAL)(1U << 7))   /* PSR: [7] */
#define WM8753_SAMPLE_256FS         ((WM_REGVAL)(0U << 7))   /* PSR: 256FS */
#define WM8753_SAMPLE_384FS         ((WM_REGVAL)(1U << 7))   /* PSR: 384FS */
#define WM8753_ADC_SRMODE_MASK      ((WM_REGVAL)(1U << 8))   /* SRMODE: Sample rate for ADC */
#define WM8753_ADC_SRMODE_SR        ((WM_REGVAL)(0U << 8))   /* SRMODE: Sample rate from SR[4:0] */
#define WM8753_ADC_SRMODE_PSR       ((WM_REGVAL)(1U << 8))   /* SRMODE: Sample rate from PSR */

/*
 * SAMPLE_RATE_CTRL_2 (0x07)
 */
#define WM8753_VXCLK_RATE_MASK      ((WM_REGVAL)(7U << 6))  /* PBMODE - [8:6] */
#define WM8753_VXCLK_MCLK_DIV_1     ((WM_REGVAL)(0U << 6))
#define WM8753_VXCLK_MCLK_DIV_2     ((WM_REGVAL)(1U << 6))
#define WM8753_VXCLK_MCLK_DIV_4     ((WM_REGVAL)(2U << 6))
#define WM8753_VXCLK_MCLK_DIV_8     ((WM_REGVAL)(3U << 6))
#define WM8753_VXCLK_MCLK_DIV_16    ((WM_REGVAL)(4U << 6))

#define WM8753_BCLK_RATE_MASK       ((WM_REGVAL)(7U << 3))  /* BMODE - [5:3] */
#define WM8753_BCLK_MCLK_DIV_1      ((WM_REGVAL)(0U << 3))
#define WM8753_BCLK_MCLK_DIV_2      ((WM_REGVAL)(1U << 3))
#define WM8753_BCLK_MCLK_DIV_4      ((WM_REGVAL)(2U << 3))
#define WM8753_BCLK_MCLK_DIV_8      ((WM_REGVAL)(3U << 3))
#define WM8753_BCLK_MCLK_DIV_16     ((WM_REGVAL)(4U << 3))

#define WM8753_VXDAC_OVERSAMPLE_64  ((WM_REGVAL)(1U << 2))   /* VXDACOSR */
#define WM8753_VXDAC_OVERSAMPLE_128 ((WM_REGVAL)(0U << 2))   /* VXDACOSR */
#define WM8753_ADC_OVERSAMPLE_64    ((WM_REGVAL)(1U << 1))   /* ADCOSR */
#define WM8753_ADC_OVERSAMPLE_128   ((WM_REGVAL)(0U << 1))   /* ADCOSR */
#define WM8753_DAC_OVERSAMPLE_64    ((WM_REGVAL)(1U << 0))   /* DACOSR */
#define WM8753_DAC_OVERSAMPLE_128   ((WM_REGVAL)(0U << 0))   /* DACOSR */

/*
 * DAC_VOLUME (0x8/0x9)
 */
#define WM8753_DACVOL_MASK          0x0FF   /* 01 = -127dB, FF = 0dB, 0.5dB steps */
#define WM8753_DACVOL_0DB           0x0FF
#define WM8753_DACVOL_MUTE          0x000

/*
 * ADC_VOLUME (0x10/0x11)
 */
#define WM8753_ADCVOL_MASK          0x0FF   /* 01 = -97dB, FF = +30dB, 0.5dB steps */
#define WM8753_ADCVOL_0DB           0x0C3
#define WM8753_ADCVOL_MUTE          0x000


/*
 * DAC Volume - _db should be between 0 and -127, -128 is mute
 * ADC Volume - _db should be between 30 and -97, -98 is mute
 * E.g. WM8753_DACVOL( 0 ) for 0dBFS, WM8753_DACVOL( -12 ) for -12dbFS.
 */
#define WM8753_DACVOL(_dB)          (WM8753_DACVOL_0DB + (2*(_dB)))
#define WM8753_ADCVOL(_dB)          (WM8753_ADCVOL_0DB + (2*(_dB)))